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I have a M.2 M-keyed slot on my laptop, and multiple M.2 PCI-e devices that I'd like to use at the same time. I've been looking for a M.2 switch or splitter of sorts but couldn't find anything, so I decided to design my own & also gain some PCI Express experience.

I tried to look up specifications for PCI Express physical layer but I couldn't find much information. Most articles I found refer to PCI-SIG website which needs a membership with a work email (that I don't have) from one of the member companies. So I tried to learn as much as possible on my own.

As far as I could figure out, a M.2 M-key slot exposes 4x PCI-e lanes. The devices I have are a combination of A/E, E and M keys. The A/E and E key devices require 1 or 2 PCIe lanes. None of the cards I have need the M.2 specific features like USB or DisplayPort. I'm also completely fine with the M-key (x4) devices running on 2 lanes or even a single lane at reduced speeds. I also learned that each PCI-e lane has a differential transmit and receive pair, and there's a reference clock that's provided by the host. So I am wondering;

  • if I design a board that would split the 4 lanes on the M-key slot out to 2 lanes on a M.2 E-key (at the matching pin numbers) plus 2 more lanes on a M.2 M-key (with the other 2 lanes N/C) and use the reference clock on both slots, would that just work?
  • Do I need to buffer the reference clock or can I just tie them together?
  • Since the I2C bus is open drain, can I just tie them all together? (Same with SMBus)
  • What does the CLKREQ# line do in PCI Express? As far as I could figure out, the PCIe card asserts this line when it needs a reference clock. Can I just pull it down, keeping all cards clocked all the time? Or can I use an OR gate so when any card plugged in needs a clock, all cards plugged in receive the reference clock?
  • What's the function of the WAKE# and PERST# lines?
  • Are there any more PCIe signals other than the TX/RX pairs, REFCLK, WAKE, PERST, CLKREQ?
  • Is there a specific power-up sequence for PCI Express?
  • Will the host detect and enumerate all devices separately, or does it need special BIOS or UEFI firmware support for this?
  • Is there anything else I should keep in mind?

I'm looking into this as more of a learning experience than just a solution for my need, so I appreciate any help I can get. Thank you!

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  • \$\begingroup\$ That bus is not designed to operate that way, even if you can get them to plug in together without blowing up, software will probably fail. That m.2 slot needs to be owned by a single device. \$\endgroup\$
    – Ron Beyer
    Commented Jun 3, 2021 at 0:53
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    \$\begingroup\$ You need a PCI-e bridge to split the lanes for you. Probably something like whatever's under the heatsink in this device. \$\endgroup\$
    – brhans
    Commented Jun 3, 2021 at 1:02
  • \$\begingroup\$ @brhans That just looks like a simple multiplexer, I instead want to split the 4 lanes for different devices and be able to use the full bandwidth for all 4 lanes. \$\endgroup\$
    – ozg
    Commented Jun 3, 2021 at 1:10
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    \$\begingroup\$ @DKNguyen I've seen full-size PCIe risers that split one 16x slot into two 8x slots with minimal circuitry (a clock buffer and a few extra components) and I'm wondering why that wouldn't be possible with M.2 M key which is basically just a PCIe x4 port. Since I should work my way up to it, and I'm looking at it as a learning experience; are there any resources that you can refer me to? \$\endgroup\$
    – ozg
    Commented Jun 3, 2021 at 1:22
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    \$\begingroup\$ @özg the x16 to dual x8 converters you mention are a completely different scenario. They use something called Slot Bifurcation in order to allow the lanes of a single slot to be split into two devices. This relies on all the lanes going back to the processor root complex, and special CPU and BIOS support - the bifurcation only works if the CPU has a root port capable of being wired as a single x16 slot or a x8/x8 or x8/x4/x4 modes. This is not something that is not available to M.2 slots, and so you would need an active PCIe switch, the datasheets for which are usually under NDA. \$\endgroup\$ Commented Jun 3, 2021 at 9:38

3 Answers 3

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if I design a board that would split the 4 lanes on the M-key slot out to 2 lanes on a M.2 E-key (at the matching pin numbers) plus 2 more lanes on a M.2 M-key (with the other 2 lanes N/C) and use the reference clock on both slots, would that just work?

Splitting lanes like this is known as "bifurcation", unfortunately there is no general requirement for hosts to support bifurcation and even when bifurcation is supported by the ICs there is often no user-accessible mechanism to control the bifurcation.

To workaround this you need what is known as a "bridge" or "switch" chip (not to be confused with simple signal switches/muxes that are also sometimes used in PCIe setups).

An example of such a chip would be the PI7C9X2G608GPBNJE. The datasheet is available but says little about how to actually turn the chip into a usable device. An evaluation board for the chip was produced but I can't find a schematic or user manual for it. Manufacturers of PCIe stuff in general seem pretty cagey about documentation.

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  • \$\begingroup\$ Thank you for the answer! By the way, another question I have is about simple signal muxes vs PCI switches. I have a mPCIe 2x Gigabit Ethernet interface card. It has two Realtek interfaces and an Asmedia AS1182e PCI bridge. I'm trying to use it on a Linux system but only one of the interfaces is usable - the other one doesn't light up at all. Google says this bridge is supported since kernel 2.6.4, but lspci doesn't show the bridge and the 2nd interface - just one interface. Do these bridges also require UEFI/BIOS support etc or do I possibly have a defective card? \$\endgroup\$
    – ozg
    Commented May 22 at 0:53
  • \$\begingroup\$ Also what would be the difference between using a digital mux vs a dedicated PCIe bridge like this? \$\endgroup\$
    – ozg
    Commented May 22 at 0:54
  • \$\begingroup\$ If you have other questions, site policy is to not ask them in an answer, but to ask a new question. \$\endgroup\$
    – MrGerber
    Commented May 22 at 9:06
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Beyond the physical layer, you have very low level kernel systems on the CPU level that you would need to write complex driver for, perhaps even rewrite the BIOS.

The I2C bus is used for some specific low-level systems and is often not implemented on consumer products, only on high-end motherboard.

Since the I2C bus is open drain, can I just tie them all together? (Same with SMBus)

No, this might disable some of the chips on the motherboard as the line may be shared for other purposes (like power supply controls, etc...).

What's the function of the WAKE# and PERST# lines?

Wake is to wake up the computer from the hardware.

Will the host detect and enumerate all devices separately, or does it need special BIOS or UEFI firmware support for this?

It does, but it doesn't necessarily knows how to communicate with them, thus the driver are required.

Is there anything else I should keep in mind?

The speed of the bus makes it difficult to work with an MCU and usually FPGA / expensive custom chip are required. There is also a lot of IP and not much information is available.

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This is supported on some desktop boards. Its called bifurcation. There are bios hacks that can work around the lack of such support on some boards that do not support it. From what I've seen it looks like its just changing the way the lanes are defined. There are a bunch of lanes of PCI express coming off the CPU and some coming off the PCH. From there its defined which slots they go to. Change that and the system thinks that they are different slots. This is commonly used with crypto miner systems where they have a large number of GPUs connected to x1 PCIe slots or on PCIe cards that have 4 m keyed m.2 slots containing 4 NVMe drives connected by x4 PCIe lanes, in x16 slot. The latter case is exactly what was inquired about. Its well known that you can use x4 PCIe devices in x2 slots. In fact I just installed one in a laptop last night. I used a 2230 drive with a b key to m key adapter in the 2240 b keyed wwan slot of a laptop. It runs with two lanes of PCIe express. Its not a stretch at all to imagine a board that goes in a 2280 slot and takes two 2230 drives. Its literally no different than the ones that go in a desktop PC.

And just to be clear, yes, the PCIe bus IS intended and designed to work that way. There is just the question of whether its supported in the bios.

Electrically, it's pretty much just this device in the link. Notice that there are some non-passive components. The single slot adapter does not have those active components. That suggests that they are more than just power or something, so you would need to understand what they do. I'd look to see if there are any PCIe to m.2 adapters and PCIe to PCIe splitters that can split out the lanes (like they use for crypto miners). And just straight up ignore the people who obviously have no idea what they are talking about. But keep in mind, once you have the hardware done, you need to deal with the software.

https://www.amazon.com/4-Disk-Expansion-Support-Protocol-Equipment/dp/B0BDQSS7P1

https://www.amazon.com/Silverstone-ECM25-NVMe-Adapter-SST-ECM25-V2/dp/B09SM5RDTQ

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    \$\begingroup\$ "And just to be clear, yes, the PCIe bus IS intended and designed to work that way" - just to clarify something, bifurcation is not part of the PCIe spec nor is there any requirement nor expectation for an upstream port to support it. It's a fancy feature of some CPUs and PCIe switch/bridge ICs, whereby they include internal virtual PCIe switching fabrics that can be reconfigured to aggregate lanes differently. I can't say I've ever come across any consumer device that allows bifurcation to anything less than a x4 link (the NVidia Jetson Orin NX has a weird x2 link that can be split in half) \$\endgroup\$ Commented Jul 29 at 22:46

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