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I have a M.2 M-keyed slot on my laptop, and multiple M.2 PCI-e devices that I'd like to use at the same time. I've been looking for a M.2 switch or splitter of sorts but couldn't find anything, so I decided to design my own & also gain some PCI Express experience.

I tried to look up specifications for PCI Express physical layer but I couldn't find much information. Most articles I found refer to PCI-SIG website which needs a membership with a work email (that I don't have) from one of the member companies. So I tried to learn as much as possible on my own.

As far as I could figure out, a M.2 M-key slot exposes 4x PCI-e lanes. The devices I have are a combination of A/E, E and M keys. The A/E and E key devices require 1 or 2 PCIe lanes. None of the cards I have need the M.2 specific features like USB or DisplayPort. I'm also completely fine with the M-key (x4) devices running on 2 lanes or even a single lane at reduced speeds. I also learned that each PCI-e lane has a differential transmit and receive pair, and there's a reference clock that's provided by the host. So I am wondering;

  • if I design a board that would split the 4 lanes on the M-key slot out to 2 lanes on a M.2 E-key (at the matching pin numbers) plus 2 more lanes on a M.2 M-key (with the other 2 lanes N/C) and use the reference clock on both slots, would that just work?
  • Do I need to buffer the reference clock or can I just tie them together?
  • Since the I2C bus is open drain, can I just tie them all together? (Same with SMBus)
  • What does the CLKREQ# line do in PCI Express? As far as I could figure out, the PCIe card asserts this line when it needs a reference clock. Can I just pull it down, keeping all cards clocked all the time? Or can I use an OR gate so when any card plugged in needs a clock, all cards plugged in receive the reference clock?
  • What's the function of the WAKE# and PERST# lines?
  • Are there any more PCIe signals other than the TX/RX pairs, REFCLK, WAKE, PERST, CLKREQ?
  • Is there a specific power-up sequence for PCI Express?
  • Will the host detect and enumerate all devices separately, or does it need special BIOS or UEFI firmware support for this?
  • Is there anything else I should keep in mind?

I'm looking into this as more of a learning experience than just a solution for my need, so I appreciate any help I can get. Thank you!

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  • \$\begingroup\$ That bus is not designed to operate that way, even if you can get them to plug in together without blowing up, software will probably fail. That m.2 slot needs to be owned by a single device. \$\endgroup\$
    – Ron Beyer
    Jun 3, 2021 at 0:53
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    \$\begingroup\$ You need a PCI-e bridge to split the lanes for you. Probably something like whatever's under the heatsink in this device. \$\endgroup\$
    – brhans
    Jun 3, 2021 at 1:02
  • \$\begingroup\$ @brhans That just looks like a simple multiplexer, I instead want to split the 4 lanes for different devices and be able to use the full bandwidth for all 4 lanes. \$\endgroup\$
    – ozg
    Jun 3, 2021 at 1:10
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    \$\begingroup\$ @DKNguyen I've seen full-size PCIe risers that split one 16x slot into two 8x slots with minimal circuitry (a clock buffer and a few extra components) and I'm wondering why that wouldn't be possible with M.2 M key which is basically just a PCIe x4 port. Since I should work my way up to it, and I'm looking at it as a learning experience; are there any resources that you can refer me to? \$\endgroup\$
    – ozg
    Jun 3, 2021 at 1:22
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    \$\begingroup\$ @özg the x16 to dual x8 converters you mention are a completely different scenario. They use something called Slot Bifurcation in order to allow the lanes of a single slot to be split into two devices. This relies on all the lanes going back to the processor root complex, and special CPU and BIOS support - the bifurcation only works if the CPU has a root port capable of being wired as a single x16 slot or a x8/x8 or x8/x4/x4 modes. This is not something that is not available to M.2 slots, and so you would need an active PCIe switch, the datasheets for which are usually under NDA. \$\endgroup\$ Jun 3, 2021 at 9:38

2 Answers 2

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if I design a board that would split the 4 lanes on the M-key slot out to 2 lanes on a M.2 E-key (at the matching pin numbers) plus 2 more lanes on a M.2 M-key (with the other 2 lanes N/C) and use the reference clock on both slots, would that just work?

Splitting lanes like this is known as "bifrucation", unfortunately there is no general requirement for hosts to support bifrucation and even when bifrucation is supported by the ICs there is often no user-accessible mechanism to control the bifrucation.

To workaround this you need what is known as a "bridge" or "switch" chip (not to be confused with simple signal switches/muxes that are also sometimes used in PCIe setups).

An example of such a chip would be the PI7C9X2G608GPBNJE. The datasheet is available but says little about how to actually turn the chip into a usable device. An evalulation board for the chip was produced but I can't find a schematic or user manual for it. Manufacturers of PCIe stuff in general seem pretty cagey about documentation.

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Beyond the physical layer, you have very low level kernel systems on the CPU level that you would need to write complex driver for, perhaps even rewrite the BIOS.

The I2C bus is used for some specific low-level systems and is often not implemented on consumer products, only on high-end motherboard.

Since the I2C bus is open drain, can I just tie them all together? (Same with SMBus)

No, this might disable some of the chips on the motherboard as the line may be shared for other purposes (like power supply controls, etc...).

What's the function of the WAKE# and PERST# lines?

Wake is to wake up the computer from the hardware.

Will the host detect and enumerate all devices separately, or does it need special BIOS or UEFI firmware support for this?

It does, but it doesn't necessarily knows how to communicate with them, thus the driver are required.

Is there anything else I should keep in mind?

The speed of the bus makes it difficult to work with an MCU and usually FPGA / expensive custom chip are required. There is also a lot of IP and not much information is available.

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