In a JFET, is the gate always connected to the bulk/substrate ? Or is there "no rule" (sometimes it is, sometimes it is not)?
And what about the case of the MOSFET ?
When a JFET is produced using the common planar process, the channel is first diffused into the bulk and, in order to insulate this region from it, the bulk is given the same doping as the gate region. Thus, a junction of the same kind as the gate-channel junction (except perhaps for the doping concentration values) is already present on the device; thus a JFET is already present. The subsequent diffusion of the gate region into the channel region creates the final, more performant device: it is like having two JFETs with the channel regions connected in parallel. At this point you have to chose if it is worth keeping the two devices separated or not. It turns out that, while it is possible to keep the two devices separated, it is better both from the point of view of performance and feasibility to make them work as one single device. In short the gate and bulk regions are hardwired together in every JFET.
A MOSFET is a 4-terminal device: gate, drain, source, and body. If you buy a discrete MOSFET it is likely that the manufacturer has connected the source to the body, but this is not required.
In your diagram the gate is not connected to the body. There is a thin insulating layer between the gate itself (colored gray) and the body underneath (colored blue).
There is no hard rule. There are many structures. Connecting the JFET gate to substrate increases the transconductance at the cost of increased gate capacitance. Connecting the substrate to the source reverses this.
On monolithic IC, the substrate is common to all devices. For the common P-type, it's normally connected to the most negative power supply. But for P-channel devices on a P-substrate, you need an "N-well" that serves as a local substrate. For CMOS digital circuits, you usually connect all the N-wells to the most positive supply, but for mixed-signal circuits it's sometimes useful to modulate the gate threshold by adjusting the N-well bias for individual transistors.
And then there are vertical MOSFETS, SOI devices, N substrates, many variations and many ways to connect them...