# Square wave frequency upsample with crystal oscillator

I'm trying to accomplish the following without the use of a microcontroller:

Input: A square wave with a 1 Hz period, duty-cycle of 100 ms (10%), normally low.

Output: A square wave with a 100 Hz period, where every period is triggered by the input wave rise event. Duty-cycle can be anything from 10 to 50%, normally low as well.

I implemented a software solution with an Arduino, but it is not precise enough. In the end, the output frequency stays anywhere from 90 to 95 Hz, instead of the coded 100 Hz. This solution listens for the input signal and triggers a timed loop to output the signal. If the input rises again, it interrupts the loop and starts again.

My question is: Is there any way to implement this with a crystal oscillator, in a way that bypasses a microcontroller solution? Or, alternatively, is there a better way to implement this and reduce latency? The interrupt routine can be neglected if the upsampled signal is precise enough.

I tried to find such a circuit or IC with similar capabilities but had no success.

• You can use a phase locked loop with a variable frequency oscillator and a frequency divider. Oct 16, 2021 at 3:28
• I feel like there is definitely something wrong with your uC code or the precision of the 1Hz clock, if you can't get a more precise output. Oct 16, 2021 at 7:25
• Frequency multiplying PLL.
– user16324
Oct 16, 2021 at 13:09

A great deal depends on the frequency accuracy and stability of your 1 Hz signal, and how much accuracy you need from your 100 Hz output.

Let's say your 1 Hz is accurate to .0001%. Then you can use a 1 MHz (.0001%) crystal oscillator to drive a divide by 10,000 counter to get 100 Hz. Make an input circuit like this simulate this circuit – Schematic created using CircuitLab

Use the reset output to sync up your divider. Use the divider to drive a second divider which produces a variable width output which is you new duty cycle.

Or, in line with Spehro's answer, you can use a slightly simpler 14-bit binary divider and a 1.6384 MHz clock, dividing the clock by 16,384.

If you take your output and divide by 100, how close is this to the input 1 Hz? If they are perfectly matched, you'll get an output clock which has a jitter (referenced to the input) of about 1 MHz. What will happen is that the counter output will accumulate error for about 100 cycles before getting reset. Whether or not the resulting odd pulse once per second is a problem is up to you, and you haven't specified your requirements.

Maybe a relatively high frequency oscillator (like 1.6348 MHz) and counter that is reset by the incoming edge, assuming the tolerance of the 1Hz is << 1%.

Using a PLL such as x4046/7046 and $$\\div\$$100 counter is possible but the lock-in time would be very long because you're only getting one phase comparison per second.