I have a digital device which transmits rapid pulses over a 3.5mm audio cable, indicating that some event has occurred. I want to connect that device to my 3.5mm line in jack on my Atlys board and determine how many of those pulses have come across. I have read some other people's questions regarding transmission, but have yet to find community sourced information on reception with the audio jacks.

The maximum pulse frequency from the device is a little under 6kHz, so I figure the Atlys board will have no problem.

I was hoping I could just monitor some "data ready" type of signal. But with the two different clocks (L15, L13) and the complexities of AC'97, for a beginner it's quite confusing.

Does anyone have any thoughts or suggestions on how I might accomplish detecting these pulses?

  • 1
    \$\begingroup\$ If you really want to use the ADC in that interface, you'll probably need code to generate the clock and control signals and shift in the data that results. However, if all you care about is counting the pulses, perhaps you can trivially condition them and accept them at a digital input. Possible even using one of the differential I/O standards (but be careful the common mode voltage you apply is legal) \$\endgroup\$ Commented Feb 28, 2013 at 14:55

1 Answer 1


Without more information all we can do is guess. You don't come right out and say whether this source of "rapid pulses" is AC'97 so my answer is going to assume it's just some arbitrary pulse train you want to look at and process. If it's AC'97 then you probably don't want to connect it to a (presumably) analog audio input.

Guess 1

The 3.5mm jack on the Atlys board has some minor signal conditioning and can be connected directly to an input pin of the FPGA. You can run that signal through a synchronizer and Bob's your uncle. Your detection time will have a resolution of the FPGA clock signal used to synchronize the incoming signal, and will have delayed by however many flip flops are in your synchronizer.

Guess 2

The 3.5mm jack on the Atlys board is treated as an analog signal (makes sense, as 3.5mm jacks are typically used for audio), conditioned as such and fed to the input of an ADC. In this case you've got to drive the ADC with the FPGA and look at the output of the ADC to determine when a pulse came in. The signal's bandwidth is only 6kHz so this really shouldn't be an issue, and you can filter the ADC data more if need be. The output of all of this should be a digital pulse train.

Guess 3

Similar to Guess 2, but maybe you're lucky and you have the analog signal from the 3.5mm jack feeding a comparator. The output of the comparator goes to the FPGA, and now you've got a digital signal that must be synchronized and used just like Guess 1.

Once you have this digital pulse train in the FPGA you probably want to count pulses over some period of time. If it's an AC'97 stream there are plenty of resources on decoding AC'97, but let's ignore the content of the data stream for the moment.

If you're just counting pulses something like this might work:

if pulse_bit changes
    if pulse_bit = '1'
    end if

end if

if pulse_timeout expires
    copy pulse count to toplevel
end if

If you're actually looking to extract some kind of intelligence from the pulse train (i.e. it's not just a pulsing line but more like a serial line and you're looking to get data from this) then you want to look at various async or sync serial ports (UART, TDM or USART) to look for the start of a transmission, grab bits and look for a stop bit. At that point you now have a data word you can look at specific bits within for what you want.

  • \$\begingroup\$ This is a pretty great answer and I appreciate your guesses. Basically, the device pulsing to the FPGA is not AC'97 and only communicates that an event has happened; it's a Geiger counter of sorts. With regard to the Atlys board, I tried synchronizing the main 100 MHz clock and the slower AC'97 clock and sampling the input. It seems that the audio input can be sampled that way, but I didn't get any indication that there was a signal on that line. \$\endgroup\$ Commented Feb 28, 2013 at 23:48
  • \$\begingroup\$ @MichaelJ.Gray ok so basically you want to get an indication of how many pulses per second/minute/hour... the code fragment can be adapted for that pretty easily, in fact. \$\endgroup\$
    – akohlsmith
    Commented Mar 1, 2013 at 0:24
  • \$\begingroup\$ So the problem is that the Atlys board's audio in doesn't have a GPIO pin or anything exposed to the FPGA which represents the line's signal. But rather, everything is processed by the AC'97 component and it makes life a hassle. All I want is an indication of if there was a pulse from the other device in the last clock or not. \$\endgroup\$ Commented Mar 2, 2013 at 3:04
  • \$\begingroup\$ @MichaelJ.Gray Ahh okay; so you then must write an AC'97 interface component (likely a master) in the FPGA, then read in the audio stream and look for the pulses. Sounds like a job for an AC'97 entity and a soft CPU core to me. \$\endgroup\$
    – akohlsmith
    Commented Mar 2, 2013 at 4:09

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