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I tried to generate 8nA from ~2uA input current using the circuit like the picture below. I use N = 16 and Iin = 2048nA. So, I am expecting 8nA output current. But somehow I got around 9.8nA.How can I make it more accurate?

enter image description here

Result

Using Cascode

EDIT: inside the box: enter image description here

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    \$\begingroup\$ Are your transistor lengths short enough to show appreciable channel-length modulation? \$\endgroup\$
    – nanofarad
    Commented Feb 15, 2022 at 20:22
  • \$\begingroup\$ @nanofarad, No, I use very long L. \$\endgroup\$ Commented Feb 15, 2022 at 20:30
  • \$\begingroup\$ I don't know what's going on exactly inside the block current source block, but it doesn't look like the diagram. All of the gates should be physically tied together on each side. You might want to show a clearer flattened schematic. \$\endgroup\$
    – pat
    Commented Feb 15, 2022 at 21:36
  • \$\begingroup\$ @pat, inside that box is a circuit like the first picture. \$\endgroup\$ Commented Feb 15, 2022 at 21:39
  • \$\begingroup\$ If that's the case, why are there external transistors? And looking at I source implies inverted device types from image. Please show flattened schematic if you can. Or take away all the external devices except IIn and just add voltage source load. Then check again. \$\endgroup\$
    – pat
    Commented Feb 15, 2022 at 21:42

1 Answer 1

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I built a very simple (nmos only matching diagram) model in ltspice.

enter image description here

Without having your exact setup and models, I can't replicate exactly. But, looking at your inner box schematic, I noticed all of your bodies are tied high. The body effect will affect the vt device matching from left side devices and right as they will not be the same. You can eliminate gamma in your model or tie bodies directly to source to verify this. Whether or not you can do this in implementation depends on your process. Other than that, you could possibly alter the series long channel length to make up for expected bias effect. I could have also played with the series device lengths to increase the long channel resistance (and matching Iout/Iin), but I didn't go that far.

My simulation shows all bodies tied to sources, as well as expected vs. sim outputs. Matching error < 2% compared to 34% with devices all tied low!

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