Under your heading
Modern FET input stage:
The image in your question is of a MOSFET circuit. As we will see, the behavior of JFETs is somewhat different from those of MOSFETs. For reference, the OPA827 from TI is designed something like this:
AFAIK, Igs of MOSFET/JFET is around 0.
That means that in MOSFET/JFET almost no current flows from gate to drain.
MOSFETs and JFETs have almost 0 gate current under normal operating conditions if the gate voltage is not varying. However, the mechanisms are different.
The gate of a MOSFET is insulated from the channel by an oxide layer. The gate of a JFET under normal operating conditions is insulated from the channel by a depletion layer. It is important to note that this depletion layer is something dynamic, depending upon operating conditions, rather than something static and material, like an oxide layer.
What about under not-so-normal operating conditions?
In an N-channel JFET, if the gate voltage is higher than the source voltage, the depletion layer no longer insulates the gate from the channel. The otherwise high impedance of the gate becomes very low. If current is not limited externally, the gate current may become excessive. However, if there is external current limiting, the JFET may be protected.
In the case of JFETs, a gate voltage which is acceptable when a circuit is powered, may result in a forward biased gate-to-channel junction when the circuit is powered off, but an input signal is still applied. Similar problems may occur in CMOS devices.
In the case of MOSFETs, an excessive gate voltage can "punch through" the thin oxide layer insulating the gate, causing high gate currents and damaging the device.
For either JFET or MOSFET inputs, clamping diodes are sometimes used at the inputs to ensure the gate voltages do not exceed rated maximum. However, the clamping diodes themselves, are subject to failure if they pass too much current. So, current limiting resistors may be helpful to protect the diodes which in turn protect the FETs.