Link to voltage supervisor

Link to AND gate

I would like to drive an open-drain output to multiple (5) loads, all of the same type.

I calculated the pull-up resistor range needed and wanted to double check to make sure this is accurate and I am able to drive all of these loads.

Circuit sketch

Here are my calculations:

  1. when output is floating high Ipullup = Ien + Ilkg Ipullup = 1μA * 5 + 1 μA = 6 μA
    Rpullup_max = Vout - Vih/Ipullup
    Rpullup_max = 3.3-2.1/6 μA = 200 kΩ max

  2. when output is low: Ipullup = Iol - Ien
    Ipullup = 1.2 mA - 6 μA
    Rpullup_min = Vout/Ipullup = 3.3/1.2 mA
    Rpullup_min = 2.75 kΩ min

So I was thinking of using a 4.7 kΩ pullup resistor for this circuit. Does this make sense?

  • \$\begingroup\$ Can you add the datasheet of the module to your question? For the case where output is low, I was expecting to see IOLmin & VIL in the calculation. \$\endgroup\$
    – sai
    Mar 15, 2023 at 17:36
  • 1
    \$\begingroup\$ Please provide the exact models of the chips you are using, preferably a link to data sheets. \$\endgroup\$
    – Justme
    Mar 15, 2023 at 18:43

2 Answers 2


The device number ISL7XCXH doesn't appear in the datasheet. I assume you mean ISL7X6CXH, since that's the only one I found in the document with a RST output that sinks up to 1.2mA.

From what I read:

  • A low input must be +0.9V or less
  • A high input must be +2.1V or more
  • Low inputs can source 1µA each
  • High inputs can sink 1µA each
  • The RST output is open-drain, able to sink 1.2mA max
  • The RST output is guaranteed to be +0.3V or less when sinking under 1.2mA

If you agree with me so far, then I say I agree with your own findings.

Sinking 6 × 1µA through a 200kΩ pull-up resistor will cause it to drop 1.2V, leaving the output at +2.1V. So 200kΩ is indeed the upper limit for that resistor. You should stay well below that.

When RST is low, it sinks 1.2mA, which must include the 6 × 1µA from all inputs, leaving only (1.2mA − 6μA) through the resistor. Whatever resistor you choose will pass maximum current when RST is at 0V, not 0.3V, so the full 3.3V will be across it. If the potential at RST rises any, current will fall, which is good.

$$ R_{MIN} = \frac{V}{I} = \frac{3.3V}{1.2mA - 6\mu A} = 2.76k\Omega $$

So we agree there too.

4.7kΩ? Yeah, that's fine.

I would also point out that another motivation for keeping R small in this setup, is input capacitance. Apparently, from the gate documentation, that's about 10pF each, for a total of 60pF. Rise time will be limited by this capacitance.

If you used a 200kΩ pull-up, the time constant will be at worst:

$$ \tau = RC = 200k\Omega \times 60pF = 12\mu s $$

That's roughly the delay between RST starting to rise, and the gates registering a change. With 4.7kΩ that drops to

$$ \tau = 4.7k\Omega \times 60pF = 0.3\mu s $$

Maybe this little delay is not a big issue for you, but it's good to keep in mind.


The following should be the constraints

  1. when output is high, your calculation seems correct.

3.3 - ((ILOAD+ILKG)*Rpullup_max) > VIH

  1. when output is low

3.3 - (IOL(min) * Rpullup_min) < VIL
This is assuming that load current is negligible compared to IOL(min). Since I do not have the datasheet, I could not calculate.


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