I am connecting a via to a polygon in one of the middle layers. My goal is to use it as a test point. Altium gives me a net Antennae violation. Although there are ways to silent the tool from giving this error, Is this something I should be worried about in terms of PCB performance?
I don't think your via will actually create an antenna.
The net Antenna rule in Altium is to make sure there are no stubs on critical nets. I usually use this rule constraints on high speed interface between a driver and a receiver.
In your case, AGND should not carry high speed signals. The error showed up because you have a thermal relief to your via and this via is not routed to anything (no load). On top of that, your net antenna tolerance is set up to only 0 mils. Hence, this creates a stub and a violation.
On a side note, if you want to reduce stub length on critical nets, you should try to put your test points in-line near the driver or receiver and use backdrilling.
Altium will flag a via going to nowhere as a net antennae. You have two options:
