How does a dual gate MOSFET reduce Miller effect?

Question

How does a dual gate MOSFET reduce Miller effect? I am trying to gain a global understaning of the physics behind them, not necessarily exact formula's that come with it other than maybe some for practical use. The Wikipedia article refers to a tetrode article based on tubes, where I get slightly lost.

I guess the questions in order are:

1. What is a tetrode (in discrete transistor/MOSFET speak);
2. How is a dual gate MOSFET similar to a tetrode, what are the 'mechanics' behind it in global terms? (Trying to get a feeling for the physics behind it).
3. How does it reduce Miller effect and is a dual gate MOSFET different from a discrete tetrode in this.
4. Is a dual gate MOSFET any good for other properties?

Answer 1

I'm going to ignore the reference to tetrode, I have never understood why an exact analogy reveals a fundamental truth.

The miller effect arises in situations from a connecting capacitance across two nodes that that have an inverting voltage gain/relationship between them. it doesn't have to be in transistors either, but in MOSFET's you have \$C_{GD}\$. How this is traditionally solved is to cascode the amplifier by isolating the offending capacitance so it doesn't appear across the gain stage. The dual gate Mosfet is basically a cascode stage with the cascode transistor built in (this has a secondary effect, see below), you just have to bias the the transistors so that they are in the active regime. M1 = amplifier, M2 = cascode

^{simulate this circuit – Schematic created using CircuitLab}

The amplifer transistor converts the input voltage in the output current and the cascode transistor simply transfers this current to the output load. the output is on the drain of the cascode and the input is on the gate of the amplifier transistor. There is no capacitance across the two nodes, the miller effect is greatly reduced.

Cascoding greatly helps in gain too.

An interesting effect from manufacturing comes into play. The upper device is a longer gate device and the lower is a dual gate device. The S/D implant to channel capacitance tends to be lower than the S/D to isolation edge capacitance (the S/D's on the outer edge) so the S/D in between the gates will tend to have a lower capacitance that if you were to have designed the circuit using two separate transistors in a cascode configuration (and obviously they take up less area). This means that the \$C_{SB}\$ capacitance is less as well making for a higher speed circuit, here SB = Source to Bulk (AKA well).

Answer 2

A dual-gate MOSFET can be used as a cascode amplifier — see Figure 1 in the Wikipedia article. By holding the "upper" gate at a fixed voltage, the effective drain voltage that the lower gate sees is also fixed, eliminating the effects of capacitive coupling to the lower gate.

Answer 3

MOSFET cascode: -

Because Q1 has very little AC signal on its source (due to the gate being decoupled), miller effect on Q2 (drain-to-gate) is greatly reduced. Q1 provides the voltage amplification due to it being injected (via its source) with AC current from Q1's drain. Q1 doesn't suffer from miller effect because its gate is decoupled.

Two MOSFETs in a row built on the same substrate is fairly trivial and this forms the dual gate MOSFET which relates to the cascode amp above, and the tetrode valve (which has control and screen gates doing the same thing).