On different well processes (fabrication process)

Question

My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the nature of fabricating wells in the twin-well and triple-well processes. My question here is about how we can use so few masks to define these wells.

Weste and Harris claim that

Wells are defined by separate masks. In the case of a twin-well process, only one mask need be defined because the other well by definition is its complement. Triple-well processes have to define at least two masks, one for the deep well and the other for either n-well or p-well.

Question:

In a twin-well process we are defining both p-wells and n-wells (inside, usually, a p-substrate). Don't we therefore need two masks to define these different wells? A similar comment would seem to imply that a triple-well process needs 3 masks?

I suppose my misunderstanding is what they mean by "masks". I am aware that a general process for defining well regions might look like (0) depending on if physical mask or pohotoresist mask can be used, grow thick oxide (1) spin positive photoresist, (2) illuminate regions which are to become wells, (3) develop, (4) if physical oxide mask is used in step 0, etch away exposed oxide regions, (5) implant and anneal. Is the idea of using a single mask that we could subsequently use this same photomask but with negative photoresist, such that when we developed and then implanted (the other dopant type) we would produce the other well type in the region which was previously covered? That is, does "mask" here refer to "photomask", the chromium-plated glass, in that the aforementioned process could use just one of these in order to achieve the desired result? The reason I am skeptical about my guess here is that this aforementioned procedure would guarantee the entire surface of the wafer would be covered by one well or the other, with no space in between them. This is in contrast with the following figure from the text, wherein there is clearly space between the wells:

Answer 1

There can be some confusion in the terminology, since in some cases the substrate (which is lightly p-doped in most CMOS ICs) counts as one of the "wells".

Single well process The two wells are (1) substrate and (2) (typically) N-well. You may define a single mask which tells where to implant N-type impurities. The regions exposed by your mask become the N-well, and everywhere else is substrate.

Twin Tub process (complementary) As suggested by Weste and Harris, we can use the complement of the N-well mask to create additional doping of the P-well beyond the substrate doping. This allows us to modify the doping of PMOS devices while having the simplicity of only one mask.

Twin Tub process (non-complementary) We can also use a separate mask to define where the additional doping should occur. This is more complex but has the advantage of allowing us to create "intrinsic" regions with relatively light doping which may be good for isolation.

Triple well process the three wells are (1) substrate, (2) N-well, and (3) Isolated P-well. You may define a single mask which creates the N-well as above, and then define a second mask to implant P-type impurities within the N-well to form the Isolated P-well.

Note 1: Single well and twin tub (complementary) processes are virtually identical from a designer's perspective. I might refer to either as a "twin well" process (perhaps incorrectly), which is the reason for the confusion in my original answer.

Note 2: Note that the diagram in your question depicts a triple well process, not either variety of twin tub.

Note 3: You can also of course do an independent P-well doping step in a triple well process (either complementary or non-complementary)