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I assigned myself a (long term) project to build an RF spectrum analyzer. In the basis it will be a super or triple (depending on frequency band) heterodyne frontend with digitized IF and some final filtering and FFT (FPGA/CPU). The idea is to add demodulation options in a later stage. I am a bit in doubt what would be the best approach for the A/D stage. The chosen A/D converter fs will be around 120 MHz. This allows an IF bandwidth of approx. 50MHz but imposes a steep anti alias filter.

Another option is to limit the IF bandwidth to 30MHz, so we have oversampling and decimate in the digital domain.

Advantages of the last option:

  • Theoretically slightly lower A/D noise floor.
  • Easier anti-alias filtering.
  • Reduced sample rate for digital filters and FFT

Disadvantages:

  • Slower sweep time (as Spectrum analyzer)
  • Half of the real time display bandwidth.

Currently I tend to go for the oversampling option. Is there any reason why this could be a bad idea for a spectrum analyzer ?

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  • \$\begingroup\$ How is this different from an SDR front end? \$\endgroup\$
    – Voltage Spike ♦
    Commented Feb 15 at 20:10
  • \$\begingroup\$ In principle not, although the requirement might be a bit different. Spurious signals might be of less importance for someone who is using an SDR just as a receiver for specific signals, whereas for a spectrum analyzer spurs should be minimal. For an SA dynamic range is important, which might be less of a concern for a receiver. \$\endgroup\$
    – Waldorf
    Commented Feb 16 at 6:13
  • \$\begingroup\$ So are you going to use a fast ADC and an FPGA? \$\endgroup\$
    – Voltage Spike ♦
    Commented Feb 16 at 16:08
  • \$\begingroup\$ 16 bit 122msps ADC + FPGA \$\endgroup\$
    – Waldorf
    Commented Apr 12 at 19:27

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