Delta Sigma (or Sigma Delta) is simply a way to convert an input value into a bitstream having the following properties:
- Average pulse density over time is the input value.
If the input value is 0.1, the output bitstream will contain on average 10% ones and 90% zeros. Many other modulation schemes also have this property like PWM, PDM, etc.
- The output bitstream looks like noise.
This is a very useful property, because it does not contain any particular frequency that may interact with other noise frequencies present in your signal. For example if you have an intrusion of mains frequency noise, sigma delta will tend to be able to ignore it, whereas fixed frequency schemes like PWM will fold and unfold it all over your spectrum like origami.
Contrast to PWM, which contain large amplitude components at the PWM frequency and its harmonics, which are difficult to filter out. PWM used as DAC also means the input value is represented as the ON time of the waveform, so the edge will necessarily shift in time depending on value, and that introduces some weird time-and phase- related artifacts.
A Delta Sigma ADC is simply a Delta Sigma DAC inside a feedback loop. It compares the analog output of the DAC with the analog input signal, adjusts the DAC's input so its output follows the analog input signal, and thus the DAC's digital input is the ADC output.
Bare Delta Sigma DACs are quite rare because when the customer wants a DAC, he usually wants an output filter too, to get an analog output and not a bitstream, so the output filter tends to be included on the chip. There are some in the "isolated amplifiers" category, because bitstreams go nicely through optocouplers, with the filter on the other side.
Anyway, the article:
If you have a resistor R and switch it with a duty cycle D... with D=0 meaning the circuit is open and D=1 meaning the resistor is always in circuit... then you get a resistor equal to R/D. Basically if the switch is closed half the time, I=U/R flows half the time, so average current is I/2R, same as with a 2R resistor. The capacitor on the bottom averages it, and the comparator measures the result.
Let's call the resistor to be measured (the one with the arrow) Rm, and the reference resistor on top is Ro.
Note, as is the schematic would be inaccurate because the resistance of the switch is in series with Ro but not with the Rm, so it adds an error equal to the resistance of the switch, which tends to not be precisely known and depend on temperature. You could use a dual channel switch chip, and put the second switch in series with the Rm to cancel the error. Charge injection is left as an exercise to the reader.
Now the weird thing is, if you replace the FPGA with a clocked flip flop, you get a sigma delta ADC acting as an ohm meter, and the work is done. If the bridge is balanced and Rm=Ro, the comparator will output a bitstream with the same number of 1's and 0's. If the bridge is balanced, and Rm is not equal to Ro, then the density of ones and zeros in the comparator output can be averaged into a duty cycle D, and we know Ro acts like a resistor Ro/D, so if the bridge is balanced, then Rm=Ro/D.
Thus you do not need special hardware: you need a flip flop and a clock to turn this into a first order delta sigma modulator (the first integration order is the cap) and you need a pulse density measurement system (ie, a counter). A microcontroller should do the job with a timer configured in counter mode. You can do more elaborate things to the bitstream, like apply a sinc filter, but averaging is a good starting point.
The maximum duty cycle is 1. Once the bitstream contains all 1's, it can't add more 1's: the modulator is clipping. So this will not work if Rm<Ro. Thus Ro should not be chosen to be equal to Rm, it should be a lower value. Ideally Ro should be half the expected value of Rm so the bitstream contains nearly 50% ones, as this is where one bit modulators are the most linear and most accurate.
