Sir, whenever i simulate my vhdl code of 4 bit counter in Xilinx vivado 2015.2, i get the error message like follwing. ERROR: [VRFC 10-724] found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+" my vhdl code is

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;

entity my_count is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; y : out STD_LOGIC_VECTOR (3 downto 0)); end my_count; architecture Behavioral of my_count is begin process(clk,clr) variable temp: std_logic_vector(3 downto 0):="0000"; begin if(clr='1') then temp := "0000"; elsif(clk='1' and clk'event) then temp := temp + 1; end if; y <= temp; end process; end Behavioral;

test bench is

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;

entity my_count_tb is -- Port ( ); end my_count_tb; architecture Behavioral of my_count_tb is component my_count port(clk,clr: in std_logic; y: out std_logic_vector(3 downto 0)); end component; signal clr,clk: std_logic; signal y: std_logic_vector(3 downto 0); begin process begin clk <=not clk after 5ns; end process; end Behavioral; please help me to solve this error