I've been trying to understand how PCIE clocking works when it comes to connecting an FPGA to a PCIE slot in a motherboard.

Looking at page 12 of this schematic for exampe: https://www.xilinx.com/support/documentation/boards_and_kits/xtp067_sp605_schematics.pdf

and following MGTRXP0 pin down to page 16 here: https://www.xilinx.com/support/documentation/user_guides/ug386.pdf

still leaves me wondering what kind of circuitry is being implemented to allow this FPGA to read TLP's at an incomming bit rate of over 2 Gbs. The only way that makes sense to me goes like this:

1. A RX buffer sampling at PCIE x1 speed reads a TLP and raises an interrupt.
2. The FPGA can then read the TLP bit by bit at whatever rate it was designed to.
3. The FPGA then writes to a TX buffer at whatever rate it was designed to, once the FPGA is done writing, the TX buffer will transmit that TLP at PCIE speed when instructed to.

Is this similar to how things work in reality?

Another related question - What kind of MCUs are involved in the PCIE chain that can transmit and sample data billions of times per second? From my very limited experience with electronics I usually encounter speeds MCUs with speeds of 1-5mhz.

Any pointers to relevant books or any other form of information would be very welcome.