Search Results
| Search type | Search syntax |
|---|---|
| Tags | [tag] |
| Exact | "words here" |
| Author |
user:1234 user:me (yours) |
| Score |
score:3 (3+) score:0 (none) |
| Answers |
answers:3 (3+) answers:0 (none) isaccepted:yes hasaccepted:no inquestion:1234 |
| Views | views:250 |
| Code | code:"if (foo != bar)" |
| Sections |
title:apples body:"apples oranges" |
| URL | url:"*.example.com" |
| Saves | in:saves |
| Status |
closed:yes duplicate:no migrated:no wiki:no |
| Types |
is:question is:answer |
| Exclude |
-[tag] -apples |
| For more details on advanced search visit our help page | |
Results tagged with synthesis
Search options questions only
not deleted
user 296228
Use this tag when you have questions regarding synthesizable code and the behaviour of the synthesis tool. Synthesis can be either for FPGA or ASIC.
10
votes
1
answer
652
views
Why is synthesis so slow compared to compilation?
Even simple HDL designs takes hours to synthesize, while compiling the Linux kernel on the same machine completes in under 15 minutes. Please explain why with a breakdown of the tasks the synthesizer …
-4
votes
3
answers
274
views
Can a digital designer beat synthesis tools? [closed]
Can we trust that a good synthesis tool will generate a netlist that is just as optimal as the first variant? … Is the answer that, for most combinational circuits, it doesn't matter if synthesis produces results that are a few percent off the optimal? …