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Results tagged with verilog
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user 78752
Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design, verification, and implementation of digital logic chips. Please also tag with [fpga], [asic] or [verification] as applicable. Answers to many Verilog questions are target specific.
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Are nested modules allowed in Verilog?
module A (input a, input b)
...
module B (input a, input b)
...
endmodule
endmodule
Is the above allowed in Verilog? …
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