I'm adjusting some vhdl code an am getting the following error:

Error (10327): VHDL error at myfile.vhd(87): can't determine definition of operator ""&"" -- found 0 possible definitions

The abbreviated code is:

port(
    input1: in std_logic_vector(1 to 1);
    ...)

signal   temp   : signed1x13;

begin
    ...
    variable slice : signed(12 downto 0);

    slice := temp(0); 
    temp <= slice(11 downto 0) & input1(0); 

As I understand it, the & operator should append a bit onto the end of the bit array slice(11 downto 0).

I've been toying with changing the data types but haven't got it working yet.

Is there something obvious I'm doing wrong?

I'm adjusting some vhdl code an am getting the following error:

Error (10327): VHDL error at myfile.vhd(87): can't determine definition of operator ""&"" -- found 0 possible definitions

The abbreviated code is:

port(
    input1: in std_logic_vector(1 to 1);
    ...)

signal   temp   : signed1x13;
-- defined elsewhere: type signed1x13   is array (1 to 1) of signed(12 downto 0);

begin
    ...
    variable slice : signed(12 downto 0);

    slice := temp(0); 
    temp <= slice(11 downto 0) & input1; 

As I understand it, the & operator should append a bit onto the end of the bit array slice(11 downto 0).

I've been toying with changing the data types but haven't got it working yet.

Is there something obvious I'm doing wrong?