I'm adjusting some vhdl code an am getting the following error:

Error (10327): VHDL error at myfile.vhd(87): can't determine definition of operator ""&"" -- found 0 possible definitions

The abbreviated code is:

    input1: in std_logic_vector(1 to 1);

signal   temp   : signed1x13;
-- defined elsewhere: type signed1x13   is array (1 to 1) of signed(12 downto 0);

    variable slice : signed(12 downto 0);

    slice := temp(0); 
    temp <= slice(11 downto 0) & input1; 

As I understand it, the & operator should append a bit onto the end of the bit array slice(11 downto 0).

I've been toying with changing the data types but haven't got it working yet.

Is there something obvious I'm doing wrong?

  • 2
    \$\begingroup\$ For one thing, input1(0) doesn't exist. That should result in a different error, but it might be confusing the compiler's operator overload resolution mechanism. \$\endgroup\$
    – user16324
    Nov 7, 2016 at 16:26
  • \$\begingroup\$ @BrianDrummond Thanks, removing the indexing from temp and input1 resultis in a mismatch error: indexed name returns a value whose type does not match "SIGNED", the type of the target expression \$\endgroup\$
    – Lee
    Nov 7, 2016 at 16:38
  • \$\begingroup\$ @BrianDrummond Question updated to take your comment into account - I get the same error \$\endgroup\$
    – Lee
    Nov 7, 2016 at 16:39
  • 1
    \$\begingroup\$ That formerly missing comment explains it, there's no overload for & that returns asigned1x13. Feel free to write one, wherever you declared signed1x13 - but it would be easier to index into temp instead. \$\endgroup\$
    – user16324
    Nov 7, 2016 at 17:05
  • 1
    \$\begingroup\$ slice := temp(1); temp <= slice(11 downto 0) & signed(input1); (There's a second error lurking in there for violating the bounds of temp). \$\endgroup\$
    – user8352
    Nov 7, 2016 at 17:56

1 Answer 1


With a couple of fixes and creating a Minimal, Complete and Verifiable Example:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity atomh33ls is
port (
    input1: in std_logic_vector(1 to 1)

end entity;
architecture foo of atomh33ls is
    type signed1x13 is array (1 to 1) of signed (12 downto 0);
    signal   temp   : signed1x13;
-- defined elsewhere: type signed1x13   is array (1 to 1) of signed(12 downto 0);

        variable slice : signed(12 downto 0);
        slice := temp(1); 
        temp <= slice(11 downto 0) & signed(input1); 
    end process;
end architecture;

Your code snippet was converted to a complete entity and architecture pair and the creation of a process where a variable can be declared.

The two fixes are the assignment to variable slice in the process where the index (0) is out of bounds for the type declaration used for temp, corrected to (1) and a type conversion from std_logic_vector to signed in the assignment to temp.

This expanded code example analyzes.

The original issue being there is no concatenation operator for a left operand of signed and a right operand of std_logic_vector. Fixing that with the type conversion to signed revealed the static bounds violation (temp(0)).


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