I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual block design:

here's what I put in the .sdc file:

create_clock -name {external_100mhz} -period 10.000000 -waveform {0.000000 5.000000} CLK_100MHZ
create_clock -name {external_12mhz} -period 83.333333 -waveform {0.000000 41.666666} CLK_12MHZ

create_generated_clock -name the_100 -divide_by 1 -source [get_pins {BLOCK.CLKA}] [get_pins {BLOCK.ClockGen.GLA}]
create_generated_clock -name the_20  -divide_by 5 -source [get_pins {BLOCK.CLKA}] [get_pins {BLOCK.ClockGen.GLB}]

and here are the warnings:

@W: MT530 |Found inferred clock ClockGen|GLB_inferred_clock which controls 169 sequential elements including BLOCK.Module.REG_DATAo[7:0]. This clock has no specified timing constraint which may adversely impact design performance.
@W: MT420 |Found inferred clock ClockGen|GLB_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:BLOCK.ClockGen_0.GLB"
@W: MT548 |Source for clock the_100 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.
@W: MT548 |Source for clock the_20 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.

1. I feel like I am close to get the syntax correct. Please, help clarifying it.

2. I see [get pins] and [get ports] - when should be used which?

3. In this answer they also put constraints on the synchronous/asynchronous aspects. In my case the external input clocks (100MHz and 12MHz) come from different oscillators, also, the GLA and GLB signal clocks are derived from the ClockGen CCC, so they are probably synchronous. Should I include the following constrains as well? Although, the external_100mhz and the_100 may be the same clock?

   set_clock_groups -asynchronous -group external_100mhz -group external_12mhz -group {the_100 the_20}

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual block design:

here's what I put in the .sdc file:

create_clock -name {external_100mhz} -period 10.000000 -waveform {0.000000 5.000000} CLK_100MHZ
create_clock -name {external_12mhz} -period 83.333333 -waveform {0.000000 41.666666} CLK_12MHZ

create_generated_clock -name the_100 -divide_by 1 -source [get_pins {BLOCK.CLKA}] [get_pins {BLOCK.ClockGen.GLA}]
create_generated_clock -name the_20  -divide_by 5 -source [get_pins {BLOCK.CLKA}] [get_pins {BLOCK.ClockGen.GLB}]

and here are the warnings:

@W: MT530 |Found inferred clock ClockGen|GLB_inferred_clock which controls 169 sequential elements including BLOCK.Module.REG_DATAo[7:0]. This clock has no specified timing constraint which may adversely impact design performance.
@W: MT420 |Found inferred clock ClockGen|GLB_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:BLOCK.ClockGen_0.GLB"
@W: MT548 |Source for clock the_100 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.
@W: MT548 |Source for clock the_20 not found in netlist. Run the constraint checker to verify if constraints are applied correctly.

1. I feel like I am close to get the syntax correct. Please, help clarifying it.

2. I see [get pins] and [get ports] - when should be used which?

3. Also the answers mentioned above use / and | when specifying source. Which one should be used when?

4. In this answer they also put constraints on the synchronous/asynchronous aspects. In my case the external input clocks (100MHz and 12MHz) come from different oscillators, also, the GLA and GLB signal clocks are derived from the ClockGen CCC, so they are probably synchronous. Should I include the following constrains as well? Although, the external_100mhz and the_100 may be the same clock?

   set_clock_groups -asynchronous -group external_100mhz -group external_12mhz -group {the_100 the_20}