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edited Sep 29, 2022 at 16:20

Null ♦

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occurred Dec 29, 2020 at 14:56

changed == to equivalent, to make it easier to read

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edit approved Dec 29, 2020 at 7:57

Shashank V M

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Is (BC + AD)<<16 ==equivalent to (BC << 16) + (AD <<16)?

Is the following equality true?expression (BC + AD)<<16 ==equivalent to (BC << 16) + (AD <<16)?

From some examples which I tried it seems to be true but not sure at all

added verilog, rtl, system-verilog and digital logic tag as it is relevant to the question; original question has verilog tag, if the verilog tag is removed people won't know this question is with respect to which languagei

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edit approved Dec 28, 2020 at 11:34

Shashank V M

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digital-logic verilog system-verilog rtl shift

removed 'assembly' and '*verilog' tags as not relevant

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edited Dec 27, 2020 at 16:40

awjlogan

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removed 'assembly' tag as it is not relevant

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edit approved Dec 27, 2020 at 16:40

Shashank V M

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Became Hot Network Question

occurred Dec 27, 2020 at 4:31

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asked Dec 26, 2020 at 19:12

MrCalc

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Is (BC + AD)<<16 ==equivalent to (BC << 16) + (AD <<16)?

Is (BC + AD)<<16 == (BC << 16) + (AD <<16)?

Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?