Why does this vintage DRAM chip enable circuit require such a beefy resistor?

Question

This is a small part of a mid-1970s chip enable circuit for a set of DRAMs. The DRAMs are TI's TMS4060 part (aka the Intel 2107 aka several others), and are 4096x1. So a typical bank requires 8 of them for 4k.

The Chip Enable input is a 12V signal. This circuit, which uses a 12V rail, uses an NPN transistor (2N2369A) plus a 130 ohm, 2W resistor to convert a TTL signal into this CE signal, and the CE line is common to all 8 chips in the bank.

(Excerpt from this schematic set, third page)

I'm pretty sure I understand the mechanism of the switching (when transistor is off, the CE line is pulled to 12V and enables the chips; when the base of transistor sees a high TTL input, the 12V goes to ground and the CE is disabled).

What I don't understand is why this massive 2W resistor is in the design-- and indeed it certainly seems to be needed, because it gets scorching hot to the touch very quickly in normal operation-- and or why this design is a good one.

In the case where it's being used as a pull-up (transistor off), I look at an example data sheet for the RAM (here's the TI) and I see Chip Enable input current max of 2μA. I multiply that by 8 for the whole bank, and get 16μA. I think what this means is that the RAM is drawing 16μA through the resistor, and that power dissipation is therefore 0.000016 * 0.000016 * 130, or a fraction of a milliwatt.

In the case where the transistor is turned on, and current is being sunk straight to ground through the resistor, then I think I'm looking at 12V*12V / 130ohms = ~1.1W (!?)

If the above math is right—and it might not be, please correct me if I've misunderstood— then I suppose it explains the 2W rating, but surely there's some better design for this sort of thing than running a mini space heater just to have your RAM chips operate.

1. Am I missing something in my understanding of the switching function of Q1?
2. Am I missing something in my understanding of the resistor sizing?
3. More to the point, is this design bananas? Why is 130 ohms burning over 1W the right choice here? For the pull-up to 12V why wouldn't you use a much higher value? Or is there some other more typical way of designing a bit of circuit here to convert from TTL levels to 0/12V such that you're not burning crazy power whenever the RAM is not enabled?

The design seems like it must be suboptimal to me, but I don't really understand why (I'm not an EE, but trying to learn!) Thanks for any insight.

Answer 1

Am I missing something in my understanding of the switching function of Q1?

No.

Am I missing something in my understanding of the resistor sizing?

Not in the value vs. supply voltage vs. power rating part.

More to the point, is this design bananas? Why is 130 ohms burning over 1W the right choice here? For the pull-up to 12V why wouldn't you use a much higher value? Or is there some other more typical way of designing a bit of circuit here to convert from TTL levels to 0/12V such that you're not burning crazy power whenever the RAM is not enabled?

No, the design isn't bananas, at least not for the mid 1970's. What you're missing is the input capacitance to the DRAM chips. I don't know what that is, but take the input capacitance to the chip, multiply it by 8 (for the 8 CE lines), add in another 50% to 150% for stray capacitance, then figure out the RC time constant -- compare that to the specified rise and fall times of the chip's CE line.

The designer chose to use a transistor driver instead of a push-pull driver for some reason. This may have been because that's what they knew, it may have been because there weren't drivers strong enough to do the job, it may have been for cost reasons (because logic was expensive back then).

Answer 2

More to the point, is this design bananas? Why is 130 ohms burning over 1W the right choice here? For the pull-up to 12V why wouldn't you use a much higher value? Or is there some other more typical way of designing a bit of circuit here to convert from TTL levels to 0/12V such that you're not burning crazy power whenever the RAM is not enabled?

I agree with TimWescott that this is a low cost way that works well enough.

But it certainly wasn't the only way. I went through a few schematics found online:

• Taito Space Invaders used 75365 Quad TTL-to-MOS Driver IC that is especially designed for the purpose, and contains a push-pull driver.
• MTU K-1008 video board uses push-pull driver made of discrete 2N3646 transistors.
• HP9830 uses Intel 3207 Quad Bipolar-to-MOS Level Shifter and Driver.
• MITS Altair 4K Dynamic RAM Board uses 7406 Six Hex Inverters with Hi-Volt Open Collector Outputs to pull the CE pin down. To pull it up, a capacitor and PNP transistor is used, which only provides a pulse of energy when the signal changes state.

The most straightforward design would have been to use an IC, the cheap way to build your own push-pull driver and the ultra-cheap way is to use a big pull-up resistor.

Answer 3

Just to expand on what has already been said, that circuit is known as a level shifter. Given the vintage, the NAND gate is most likely a TTL circuit and produced logic output voltage levels of 0-5 V. The TMS4060 required a 0-12 V logic swing, so the discrete (non-integrated circuit, but individually packaged transistor and resistor) implemented an RTL inverter, powered by 12 V. As mentioned the entire capacitance of the circuit must be pulled up through the resistor in the desired enable time of the system, so that defines the RC time constant and hence the resistor's value. Once the resistor's value is known, the current saturation and power dissipation of the transistor is determined. As the heat of the resistor attests, that power was beyond the power handling ability of TTL gates, (they couldn't use a TTL 7438, an open collector NAND gate) hence the need for larger discrete parts. I'm guessing 2N3904 or 2N2222?

I just checked your attached schematic and parts list. It's a bit bogus. Dunno if it's sloppiness or intentional obfuscation. But the transistor which is drawn (and should be) an NPN transistor to function properly as a level shifter, is listed as an 2N2269A, which is a PNP transistor. And the NAND gate driving the transistor is listed as part of 7408, a quad AND gate. Weird.

Answer 4

The circuit is a basic saturating transistor inverter. It has to be reasonably fast. The lower the collector resistor, the faster it will turn off, for two reasons:

1. The higher on-state collector current requires more base current and thus will dissipate the base charge quicker.

2. The lower collector resistor will swing any attached capacitive loads faster than a higher one.

The RC time constant does not care about supply voltage - thus, for the RC-borne switching delay, it is the resistor value that matters. If it has to dissipate a lot of power - too bad, so sad, you have to live with it.

What I don't understand is why this massive 2W resistor is in the design

It's not like someone decided "let's waste 2W of power". The design constraints are:

1. Drive high enough current into the collector, to desaturate Q1 quickly.

2. Get the R C_load time constant low enough.

For both of those reasons, R needs to be low. That it ends up dissipating 2W - oh well.

I see Chip Enable input current max of 2μA

Static pin input current is only relevant in static DC power dissipation analysis. In figuring out the performance of this transistor inverter, the static CE current has no influence whatsoever on the design process. Nothing much would change if that current was 100x higher. The design is about speed, and the currents involved are orders of magnitude higher than 2μA x 8.

The design seems like it must be suboptimal to me

If a young player was designing the circuit, I bet you he started with a 4k7 or 1k resistor, and nothing worked, and got his eureka moment once it was figured out. The young player was trying not to make things scorching hot either :) This "dissipation vs speed" issue has bitten a lot of EEs over the decades - so many, that it's a certainty that the above scenario happened many times over.

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For sake of simplicity, assume that each DRAM's CE pin capacitance is about 15pF, plus about 50pF of distributed trace capacitance. That's about 0.2nF of capacitive load hanging on the collector of Q1:

^{simulate this circuit – Schematic created using CircuitLab}

Now let's see how fast a 2N2222 will switch with such a load. Looks like a bit under 100ns.

Now for a 2N3904 - the stored base charge and higher gain makes things worse:

For the pull-up to 12V why wouldn't you use a much higher value?

Because it doesn't work, that's why:

^{simulate this circuit}

Things get positively glacial. 0.6μs is a long time to wait for an inverter to do its job. It is only about 500x faster than reed relays! The fast ones switch in about 0.2ms.