Synchronous Buck High Side Driver - Why is the Fall Time of High-Side Gate Drive so Slow?

Question

Below is the picture of my gate drive signals. The blue trace is the low side gate signal and the yellow trace is the high side gate signal. Both signals are measured across the gate and source of the high and low side mosfets.

As you can see the high-side gate signal (yellow trace) is falling very slowly. Why is this the case? I am using an NCP5181 as my gate driver.

Below is my circuit.

For completeness, below is the block diagram of my gate driver IC. In the block diagram of the datasheet it shows that the high side is driven low by a push-pull MOSFET configuration so I would think that the gate signal should go low quickly.

For reference here are the scope signals when they are both measured with reference to the ground of the circuit.

Answer 1

Comment from the OP: -

The probes are connected between the gate and source of both MOSFETs directly.

Here's where you are likely screwing up. The ground connection on the probes are connected to each other to local ground on the oscilloscope so, in-effect, you are shorting out the lower MOSFET from drain to source.

If you want to do this properly use two probes that have their ground connection to 0V on the target circuit and probe the gate and the source of the top MOSFET. Look at the differential voltage by using the appropriate function on the o-scope.

Make sure both o-scope channels are set to DC.

Answer 2

This usually happens when designers fail to recognize the impedance ratios of RdsOn of the gate driver and RdsOn of the power switch.

But in your case with updated info your gate resistor is too high and Boost cap may be too low or commutation rate.

Replace 100 ohms with 5 Ohms to closer to matched driver impedance as long as the Boost cap is not decaying too fast.

It is a known characteristic that the gate charge Q and Ciss is inversely proportional to RdsOn. This also applies to Coss. So when commutation occurs you have a nonlinear C near Vth threshold of Vgs that rises sharply when turning on after some latency period.

The other known characteristic is some bridge drivers tend to have higher Rdson for Pch/Nch ratios. In this case ratio=2.5x nominal and lower worst case at max RdsOn. However since your question and design is incomplete, the ratios of Ciss for your output stage need to be factored with the model of driver impedance. I won't draw the model, but it is like a switched capacitance at threshold of switched resistance. So one would expect using this chip that the high side will be slower turn ON and turn OFF than the low side.

Great care must be taken in choosing your power drivers for many parameters affect RdsOn, Ciss and Coss such that the figures of merit FoM are the time constants RC=T for different stages, off, transition and On.

I prefer to start by ensuring the Power Switch RdsOn is not less than 1% of the prior stage RdsOn for fast gate transition times. But in high power devices this must be drive/output switch resistance ratio may need to be increased to 10%, which is why IGBT's are more popular having exceptionally low output RC= Times for the BJT output and with equally low input. T= Ciss *Rg thus fast slew rates for the low current MOSFET inputs.

Review your design in light of these parameters and please improve the details in your overall design with full schematic, layout and loads.

Finally where the output drive not shown is wired OR, you must ensure the results of Gate driven T slew rates do not reduce the dead-time needed to prevent shoot-thru and thus are momentary break before make on the order of 1us +/- 50% or more depending on RdsOn/L load.