What does the "posted" mean in posted PCIE transaction?

Question

What is the etymology of the word "posted" in "posted PCIE transaction"? I've worked with PCIE and I understand the difference between "posted" and "non-posted" PCIE transactions, but I don't understand what the word "posted" means. Where does "posted" come from? What does it really mean?

Answer 1

I know little about PCI, but it looks to me that the main thing about posted transactions is that you don't have control over them once they're initiated.
A bit like sending a message by mail (post!): once the message is in the mailbox it's beyond your control.
Other systems also use post, e.g. the Windows messaging system knows posting and sending. When sending a Windows message you're in control until the message has been handled, when posting you place it in the message queue, and that's it. No feedback, no acknowledging.

Answer 2

To know about PCIe Posted Transactions, you have to understand what a "posted write" is for legacy PCI, and what a legacy PCI read is.

For a legacy PCI read, and indeed reads on most busses, the CPU sends out a read command and the read address then waits for the device to respond with the data and a "Done" signal of some kind. Basically is is a Command and Response type thing.

Normal writes on a legacy PCI bus, and many other busses, is similar except that the command is the write signal + address + data and the response is just a "done". The problem with this is that for many systems the "done" is not needed and just takes time. If the peripheral you're writing to can accept writes at full speed then the done is not at all needed.

A "posted write" is a write that does not wait for a "done". The CPU assumes that the write cycle will complete with zero wait states, and so doesn't wait for the done. This speeds up writes considerably. For starters, it doesn't have to wait for the done response, but it also allows for better pipelining of the datapath without much performance penalty.

In PCIe land all writes are posted. But PCIe calls them "posted transactions" because there are many types of writes (memory writes, I/O writes, configuration writes, etc.). There are also a couple of other transactions that don't have a response.

The reason why all writes are posted is because the serial and packet based nature of PCIe makes the "response" super slow. It is common for a single word read to take several microseconds to complete. So, even though the bus is running at 2.5 gigabits/second you could only get about 4 megabytes/second if doing single word reads. Change that to single word posted writes and the bandwidth will go up to around 60 megabytes/second. Change to multi-word posted writes and you're up to about 250 megabytes/second.

There is no such thing as a posted read, on any bus, because all reads require a response (a.k.a. the data you're reading).

Answer 3

It helps to understand that a PCI bus controller forms an interface between a processor local bus, i.e., the CPU's native bus structure, and the PCI adapter bus. Suppose your CPU wants to write data to a PCI device; there aren't device-selects running directly from your native bus address decoder out to a plugged-in PCI card, so what happens is that the CPU writes to a portion of its local physical address space that is decoded to the PCI bus controller. When the PCI bus master sees the write-cycle, it latches the address and data, at which point the rest of the I/O transaction is decoupled from the CPU. The CPU is free to go on its way, do the next thing, b/c at this point, the cycle has been 'posted' to the PCI bus controller; the PCI bus controller then manages selecting the correct device and finishing the I/O cycle.