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how are you all doing?

I have been experimenting with the Colpitts Oscillator and encountered a minor issue that I would like to resolve. Here are the two circuits - the first one is working flawlessly, while the second one isn't. Notice that the BJT biasing is exactly the same for the both of them.

First Circuit (Working)

Circuit #1

Second Circuit (Not Working)

enter image description here

It is interesting to note that the circuit is oscillating in the LTSpice simulation.

Simulation

What is the issue with the second one - as it is a textbook example? I would really like to know, thanks!

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    \$\begingroup\$ VDD shorted to output is not a good start. Which textbook? \$\endgroup\$
    – user16324
    Commented Jun 19, 2020 at 20:17

2 Answers 2

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Your 2nd circuit is indeed wrong. You have shorted out where the collector resistor should be. In effect, the collector is tied to Vdd despite you also calling that node “output”.

And, while you are fixing it, get rid of C3 because it puts an AC short from base to Vss.

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  • \$\begingroup\$ Thank you very much for the quick response Andy! I have revised the circuit per your suggestions, and placed a 100uH Choke instead the Collector resistor. The circuit still isn't working. Should I use a choke with a larger value, or replace it with a resistor? imgur.com/a/uecJtE5 \$\endgroup\$
    – George
    Commented Jun 19, 2020 at 20:19
  • \$\begingroup\$ R3 should be bypassed with a cap, there's not enough gain now. \$\endgroup\$
    – user136077
    Commented Jun 19, 2020 at 20:25
  • \$\begingroup\$ @George now you have the collector DC connected to the base via the inductor and this will mess with things I suspect. Try putting a 1 nF capacitor in series with the inductor. \$\endgroup\$
    – Andy aka
    Commented Jun 19, 2020 at 20:33
  • \$\begingroup\$ It worked like a charm Andy, thanks! I will let you know if the capacitor affects the output! imgur.com/a/HGIXKiN \$\endgroup\$
    – George
    Commented Jun 19, 2020 at 20:38
  • \$\begingroup\$ @George that's good but don't formally accept this answer yet, wait to see if you get better answers. \$\endgroup\$
    – Andy aka
    Commented Jun 19, 2020 at 20:41
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At 50MHz, you need a 0.1uF capacitor bypassing your VDD to your VSS.

And that new capacitor now is part of the circulating_energy path of your resonant loop.

Thus any external trash (shared VDD traces) ends up modulating your oscillator, making the Local Oscillator become an FM_signal_generator

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