I found the following data slicer circuit:
simulate this circuit – Schematic created using CircuitLab
The input is a simple NRZ (PAM-2) signal between "Vhigh" and "Vlow" (=around 0V) where each bit has a length "Tbit". Due to bandwidth limitation, the input is also not a perfect square pulse but can be modeled as being filtered with a simple first-order lowpass with cutoff "fc".
I can't wrap my head around why exactly the author or this circuit came up with the idea of adding R1+C1 (and R3). I cannot find a single where adding R1+C1 would not make things worse (after all, it's a highpass/differentiator). Similarly, I neigher see the purpose for R3, nore can I find a case where it would be helpful.
In LTspice, the circuit works best if I kick out R1,C1 and R3 and make R2*C3 = 5/Tbit (as suggested in https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3671.html).
But I don't want to remove just just because I don't understand it...
EDIT: Maybe this was a "hard" question so I changed it to merely understand what this thing is doing...