Verilog implementation - variable range error for a register assignment

Question

I am trying implement the following idea in Verilog. I tried giving variable range and got an error that error must be bounded by constant values.

There is an 8-bit register which gets updated on every clock cycle. I am required to incrementally take values from this register i.e.
reg[0] in the first iteration,
reg[1:0] in the second iteration,
reg[2:0] in the third iteration
and so on. The output from this register along with a decreasing number of zeros are given to a 12 bit register i.e
{reg[0],11'b00000000000} in the first iteration,
{reg[1:0],10'b0000000000} in the second iteration,
{reg[2:0], 9'b000000000} in the third iteration.
How do I generalize this ?

My original code:

module FGen (Clk, Reset, F, Aplusone, sjplusone);

input logic Clk;
input logic Reset;

input logic [1:0] sjplusone;
output logic [11:0] F;
output logic [7:0] Aplusone;

logic [7:0] K, A, B, Bplusone;
logic [7:0] Z;
logic Kout;
int count = 0;

assign A = 8'b00000000;
assign B = 8'b00000000;
assign Z = 8'b00000000;

shiftreg #(8) shr (Clk, Reset, Load, 1'b1, 8'b11111111, K, Kout);
mux2 #(8) m1 ({A[6:0], Kout}, {B[6:0], ~Kout}, sjplusone[1], Aplusone);
mux2 #(8) m2 ({B[6:0], Kout}, {A[6:0], ~Kout}, ~sjplusone[1], Bplusone);
mux2 #(12) Fmux ({2'b11, ~Aplusone[count:0],Z[8-count:0]}, {2'b00, Bplusone[count:0] - 1'b1,Z[8-count:0]}, sjplusone[1], F);

assign count = count + 1;

endmodule

Answer 1

It would really help to show the code you wrote as your attempt and how it is supposed to iterate, as well as the exact error, but I think you just need a logical shift left.

logic [7:0] reg8;
logic [11:0] reg12;
int iterator;  // goes from 0 to 7

// each iteration
  reg12 = reg8 << 11-iterator;