I'm a beginner at FPGA design and have been actively trying to complete new projects to get more hands on experience.
The project I'm currently working on is a tutorial from nandland. This video project was designed for the GoBoard, but I'm using a DE10-Lite. Quick project descriptions:
- Converts the ASCII input into Hex on the 7-segment
- Receives input from the keyboard (via UART)
The problem is that I can't seem to figure out how to use keyboard as an input. I used TeraTerm as a terminal emulator and created a USB to UART module as posted below, but no input is detected (I think). Am I missing something? Do I need to assign the input signal in Pin Planner?
I'm almost certain that the problem is that TeraTerm can't communicate with the FPGA since the USB Blaster isn't on the Ports list. It's only in the "Universal Serial Bus controllers" of Device Manager. The only 2 options on the Ports list is COM1 and COM3, both of which still appear on the list even after I've removed the USB Blaster. How would I get TeraTerm to connect to the correct port? Or even more useful, is there a better/easier workaround to emulate the Terminal?
Initially I wrote the majority of the HDL itself I used the video solely as a project outline and to understand the block diagram. But after running into the problem, I've essentially copied the source code almost entirely to determine if my own code was the problem. This didn't fix the problem either. After some debugging, I've confirmed that the Binary to 7 Segment module was working correctly (tested by using the on-board switches as inputs), so the the problem either lies within in USB to UART module, or something else that I've missed.
USB to UART Module:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UART_RX is
generic (
g_Clk_Per_Bit : integer := 434
);
port (
i_Clk : in std_logic;
i_RX_Serial : in std_logic;
ow_RX_Check : out std_logic;
ow_RX_Data : out std_logic_vector(7 downto 0)
);
end entity UART_RX;
architecture RTL of UART_RX is
type t_SM_Main is (s_Idle, s_RX_Start, s_RX_Data,
s_RX_Stop, s_Reset);
signal r_SM_Main : t_SM_Main := s_Idle;
signal r_Clk_Count : integer range 0 to g_Clk_Per_Bit - 1 := 0;
signal r_Bit_Index : integer range 0 to 7 := 0;
signal r_RX_Data : std_logic_vector(7 downto 0) := (others => '0');
signal r_RX_Check : std_logic := '0';
begin
p_UART_RX : process (i_Clk)
begin
if rising_edge(i_Clk) then
case r_SM_Main is
when s_Idle =>
r_RX_Check <= '0';
r_Clk_Count <= 0;
r_Bit_Index <= 0;
if i_RX_Serial = '0' then
r_SM_Main <= s_RX_Start;
else
r_SM_Main <= s_Idle;
end if;
when s_RX_Start =>
if r_Clk_Count = (g_Clk_Per_Bit - 1)/2 then
if i_RX_Serial = '0' then
r_Clk_Count <= 0;
r_SM_Main <= s_RX_Data;
else
r_SM_Main <= s_Idle;
end if;
else
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Start;
end if;
when s_RX_Data =>
if r_Clk_Count < (g_Clk_Per_Bit - 1) then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Data;
else
r_Clk_Count <= 0;
r_RX_Data(r_Bit_Index) <= i_RX_Serial;
if r_Bit_Index < 7 then
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_RX_Data;
else
r_Bit_Index <= 0;
r_SM_Main <= s_RX_Stop;
end if;
end if;
when s_RX_Stop =>
if r_Clk_Count < (g_Clk_Per_Bit - 1) then
r_Clk_Count <= r_Clk_Count + 1;
r_SM_Main <= s_RX_Stop;
else
r_RX_Check <= '1';
r_Clk_Count <= 0;
r_SM_Main <= s_Reset;
end if;
when s_Reset =>
r_RX_Check <= '0';
r_SM_Main <= s_Idle;
when others =>
r_SM_Main <= s_Idle;
end case;
end if;
end process p_UART_RX;
ow_RX_Check <= r_RX_Check;
ow_RX_Data <= r_RX_Data;
end architecture RTL;
Thanks for your input!
