Does a SAMD21 microcontroller have internal current limiting on the GPIO?

Question

I am using the SAMD21 microcontroller which at full drive strength source = 7mA and sinks= 10mA at 3.3v. Im going to drive a mosfet directly

Do i need to place a large gate resistor to limit the current to those values? or there is already a current limiting done inside the chip?

3.3v at 7mA is a 471 Ohm gate resistor. My mosfet is rated at 3nC. Which seems to be very high for a gate resistor,

at 7mA gate current and 3nC gate charge im getting 1.1MHZ of switch time which is still above my required switch frequency

Answer 1

GPIO does not have current limiting. But the transistors are limited in their capability.

What you need to look out for is not exceeding the maximum rating. Which is at the highest drive settings at high level, 7mA continuous. (assuming all other Vdd clusters specs are met)
In this state the output voltage will be at least 0.8*Vdd (2.64V)
This state also adds 5 mW to the total package power.

I can't find an absolute maximum rating for any IO pin, but injection limit is 15mA.

With a mosfet you are basically driving a capacitor. If you keep it under the 7mA, take 390, if you try to keep it under 15mA, take 220 Ohm. ​ Note that you would want to get a mosfet with a Vgsth of 2.7-3v or better.

If you ever want to slow down the switching time for EMC noise reasons this resistor is a good place to start.

Answer 2

There is generally no current limit on MCU IOs. There is a max. continuous DC current rating (7 mA in this case). IOs are designed to drive (small) capacitor loads - when toggling, the peak current will exceed this 7 mA level (consider also that 7 mA is a typical or worst case spec -- under other conditions, the current may significantly exceed this value).

There are two limitations you should consider for the loads you can use -- one is total power dissipation in the MCU, the other is some 'average' of the output current.

1. Power dissipation: If you drive 3 nC at 1 MHz from 3.3 V (with no external gate resistor), the power dissipated in the MCU will be C.V.f = 3n3.31M = 10 mW (Note this is independent of the actual drive strength). 10 mW is probably not a concern.

2. 'Average' current: This is related to wearout (electromigration) of the metal lines inside the MCU. If you drive at 1 MHz, and don't use an external resistor, the peak current could be in the 50 mA range. This would charge the 3 nC in about t=Q/I=60 ns (very approximate -- we are looking for worst case numbers here). Thus at 1 MHz, you could have 50 mA flowing for 60 ns (charging), and also 50 mA for 60 ns (discharging). Thus the rms current is (worst case approximate calculation) 50mAsqrt(120n1M) = 17 mA. This is significantly above the 7 mA spec, and would warrant further investigation if used in a commercial project. In a hobby project, it is probably not an issue.

A mitigation you could use is to tie two IOs in parallel and drive simultaneously. This would reduce the individual currents by half.

Answer 3

The I/O pad will have a minimum ‘on’ resistance, Rds(on). This will be a kind of inherent current limiting.

You can calculate this from the output high / output low (Voh, Vol) at the rated pad current. For example, with the output-low sinking 10mA and assuming 660mV low, that would be 66 ohms maximum. Nominal value could be half that.

There will also be a total package limit for current sink/source for all the pins collectively.

Related: Finding maximum sink and source currents from datasheet

If your FET turn-on and turn-off times are a concern you may consider adding a gate driver to your design. This will improve efficiency as it will avoid the FET being in the linear zone. Further, the driver can be used to increase the FET Vgs drive voltage and reduce the FET on resistance. At 1.1MHz both issues will be important.