What does the speed of calculating the Fir filter depend on in the
Dsp?
It depends on many factors, the clock, how fast you are sampling from the ADC, if there are memory delays, size of the filter (and implementation, like symmetric or direct which have tradeoffs vs operations and memory) ect. The implementation will also depend on how many adds/ multiplies you have. Each multiply and add operation (or there are also special operations that do both on the TI processors) also will have X amount of clock cycles per instruction. There are entire courses taught on how to calculate the filter and delay for an FIR filter on one of these processors and implement it. Probably the slowest thing will be the ADC or getting data to and from the ADC.
In which unit of the DSP are these calculations performed?
Depends on which instructions you use, the processor you have listed has six ALU's and one processor (AFAIK), the instructions tell it which processor to use.
When calculating the processing rate of the filter, should I look
where it says MHz?
You can estimate the time if you know the size of the filter, if you have a 32 tap direct form FIR, you'll need about 32 delays (memory elements) and about 32 multiply-add operations. So if a multiply add takes 1 clock then it would be the clock frequency divided by 32, plus whatever the memory operations take. But at the end of the day it's really the phase of the realized filter form that matters.
So I would start by looking at the filter you want to implement, and look at the phase and tap requirements for that.