I'm a beginner to both KiCAD and PCB design. I'm using KiCAD 6.0 on a mac. I'm trying to learn simulation and although the simulation basics seem straightforward enough, I have trouble importing models.
The above is my sample circuit. Now, it may include obvious flaws that I'm missing, since LM2776 is a new part for me, but I tried to make it similar to how its use is described on the datasheet. I'm planning to use it though in my circuits so I'd like to simulate its function before I try it out on the breadboard - I skipped the decoupling caps since I thought I wouldn't need them due to the noise-free current.
I used the built-in LM2776 symbol, but got the SPICE model from UltraLibrarian, which seems to be the official TI one. I chose the LM2776_TRANS model in the SPICE library.
If I understand correctly, the SPICE model's pinouts are described on this line:
.SUBCKT LM2776_TRANS Cn Cp EN VIN VOUT GND
so I defined the alternate node sequence thus: 6,5,4,3,1,2
I also switched the compatibility mode to PSpice. I would have included the SPICE model itself here as well, but SE the character limit ran out.
... but as you can suspect, it didn't work. The simulator's output was thus:
Compatibility modes selected: ps
Circuit: KiCad schematic
Reducing trtol to 1 for xspice 'A' devices
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Note: Starting true gmin stepping
Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Last gmin step failed
Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: True gmin stepping failed
Note: Starting dynamic gmin stepping
Trying gmin = 1.0000E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 5.6234E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 8.6596E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.6466E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9105E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9775E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9944E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9986E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Further gmin increment
Trying gmin = 9.9996E-03 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Last gmin step failed
Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: Dynamic gmin stepping failed
Note: Starting source stepping
Supplies reduced to 0.0000% Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Trying gmin = 1.0000E-02 Warning: singular matrix: check nodes unconnected-_u1-pad4_ and unconnected-_u1-pad4_
Warning: gmin step failed
Warning: source stepping failed
Transient solution failed -
Last Node Voltages
------------------
Node Last Voltage Previous Iter
---- ------------ -------------
net-_v1-pad1_ 0 0
net-_c1-pad1_ 0 0
net-_c1-pad2_ 0 0
xu1.n17015088 0 0.00455991 *
xu1.e 0 -0.00911982 *
xu1.en_ok 0 0
xu1.e_abm4_int1 0 0
xu1.n16871772 0 0.00455991 *
xu1.n16760001 0 0
xu1.phi1 0 0
xu1.e_abm2_int1 0 0
xu1.phi2 0 0
xu1.shdn 0 0
net-_r2-pad2_ 0 0.00455991 *
xu1.g_abmii4_int1 0 0
unconnected-_u1-pad4_ 0 0
xu1.ishdn 0 0
xu1.quies 0 0
xu1.n17384594 0 0
xu1.e_abm8_int1 0 0
xu1.e_abm3_int1 0 0
xu1.phi 0 0
xu1.cpump 0 0
xu1.x_u2.inp1 0 0
xu1.x_u2.inm1 0 0
xu1.n16760455 0 0
xu1.x_u2.inp2 0 0
xu1.x_u2.ehys_int1 0 0
xu1.x_u2.1 0 0
xu1.n16760389 0 0
xu1.x_u2.eout_int1 0 0
xu1.n17384614 0 0
xu1.g_abmii2_int1 0 0
xu1.prech_pulse 0 0
xu1.n17221946 0 0
xu1.u2_ctrl_rdiv 0 0
xu1.u2_ctrl_n16844013 0 0
xu1.x_u2_ctrl_u10.yint 0 0
xu1.x_u2_ctrl_u10.e_abmgate_int1 0 0
xu1.u2_ctrl_uvlo 0 0
xu1.u2_ctrl_n16785976 0 0
xu1.u2_ctrl_n16842955 0 0
xu1.x_u2_ctrl_u3.inp1 0 0
xu1.x_u2_ctrl_u3.inm1 0 0
xu1.u2_ctrl_thres_offset 0 0
xu1.x_u2_ctrl_u3.inp2 0 0
xu1.x_u2_ctrl_u3.ehys_int1 0 0
xu1.x_u2_ctrl_u3.1 0 0
xu1.pfm 0 0
xu1.x_u2_ctrl_u3.eout_int1 0 0
xu1.x_u2_ctrl_u18.yint 0 0
xu1.x_u2_ctrl_u18.e_abmgate_int1 0 0
xu1.u2_ctrl_n16785492 0 0
xu1.x_u2_ctrl_u9.yint 0 0
xu1.x_u2_ctrl_u9.e_abmgate_int1 0 0
xu1.x_u2_ctrl_u2.inp1 0 0
xu1.x_u2_ctrl_u2.inm1 0 0
xu1.u2_ctrl_n16786076 0 0
xu1.x_u2_ctrl_u2.inp2 0 0
xu1.x_u2_ctrl_u2.ehys_int1 0 0
xu1.x_u2_ctrl_u2.1 0 0
xu1.u2_ctrl_n16786106 0 0
xu1.x_u2_ctrl_u2.eout_int1 0 0
xu1.e_abm7_int1 0 0
xu1.pi 0 0
xu1.ilim 0 0
xu1.n17512460 0 1e-14
xu1.x_u21.yint 0 0
xu1.x_u21.e_abmgate_int1 0 0
xu1.n16759705 0 0
xu1.n16759819 0 0
xu1.x_u4.inp1 0 0
xu1.x_u4.inm1 0 0
xu1.x_u4.inp2 0 0
xu1.x_u4.ehys_int1 0 0
xu1.x_u4.1 0 0
xu1.n17345547 0 0
xu1.n17324527 0 0
xu1.x_u4.eout_int1 0 0
xu1.ilim_comp 0 0
xu1.n17385154 0 0
xu1.n17495282 0 0
xu1.n17549214 0 0
xu1.e_abm11_int1 0 0
xu1.x_u22.qint 0 0
xu1.x_u22.gq_int1 0 0
xu1.n16759799 0 0
xu1.x_u22.my5 0 -0.0498103 *
xu1.x_u22.myvss 0 0
xu1.x_u22.qqq 0 0
xu1.x_u22.x3.yint 0 0
xu1.x_u22.x3.e_abmgate_int1 0 0
xu1.x_u22.qqqd1 0 0
xu1.x_u22.qbr 0 0
xu1.x_u22.eqb_int1 0 0
xu1.n16759875 0 0
xu1.x_u26.qint 0 0
xu1.x_u26.gq_int1 0 0
xu1.n17522872 0 0
xu1.n17324921 0 0
xu1.x_u26.my5 0 -0.0498103 *
xu1.x_u26.myvss 0 0
xu1.x_u26.qqq 0 0
xu1.x_u26.x3.yint 0 0
xu1.x_u26.x3.e_abmgate_int1 0 0
xu1.x_u26.qqqd1 0 0
xu1.x_u26.qbr 0 0
xu1.x_u26.eqb_int1 0 0
xu1.n17525531 0 0
xu1.n17391639 0 0
xu1.x_u27.yint 0 0
xu1.x_u27.e_abmgate_int1 0 0
xu1.n17548583 0 -1e-14
xu1.n17548547 0 0
xu1.n17551684 0 0
xu1.n17551687 0 1e-14
xu1.e_abm12_int1 0 0
xu1.x_u15.yint 0 0
xu1.x_u15.e_abmgate_int1 0 0
xu1.n17324922 0 0
xu1.x_u25.yint 0 0
xu1.x_u25.e_abmgate_int1 0 0
xu1.e_abm6_int1 0 0
xu1.x_u_osc_u131.yint 0 0
xu1.x_u_osc_u131.e_abm_int1 0 0
xu1.u_osc_n16690266 0 0
xu1.u_osc_n16690364 0 0
xu1.u_osc_muxclk 0 0
xu1.x_u_osc_u134.yint 0 0
xu1.x_u_osc_u134.e_abmgate_int1 0 0
xu1.u_osc_n16690380 0 0
xu1.u_osc_n16690352 0 0
xu1.u_osc_n16690808 0 0
xu1.x_u_osc_u135.e_current_int1 0 0
xu1.u_osc_n16690502 0 -0.0498103 *
xu1.x_u_osc_u136.x1.yint1 0 0
xu1.x_u_osc_u136.x1.e_abmgate1_int1 0 0
xu1.x_u_osc_u136.x1.yint2 0 0
xu1.x_u_osc_u136.x1.yint3 0 0
xu1.x_u_osc_u136.x1.e_abmgate2_int1 0 0
xu1.x_u_osc_u136.clkdel 0 0
xu1.x_u_osc_u136.x2.yint 0 0
xu1.x_u_osc_u136.x2.e_abmgate_int1 0 0
xu1.x_u_osc_u136.clkint 0 0
xu1.x_u_osc_u136.qint 0 0
xu1.x_u_osc_u136.gq_int1 0 0
xu1.u_osc_n16690232 0 0
xu1.x_u_osc_u136.my5 0 -0.0498103 *
xu1.x_u_osc_u136.myvss 0 0
xu1.x_u_osc_u136.qqq 0 0
xu1.x_u_osc_u136.x3.yint1 0 0
xu1.x_u_osc_u136.x3.e_abmgate1_int1 0 0
xu1.x_u_osc_u136.x3.yint2 0 0
xu1.x_u_osc_u136.x3.yint3 0 0
xu1.x_u_osc_u136.x3.e_abmgate2_int1 0 0
xu1.x_u_osc_u136.qqqd1 0 0
xu1.x_u_osc_u136.qbr 0 0
xu1.x_u_osc_u136.eqb_int1 0 0
xu1.x_u_osc_u132.yint1 0 0
xu1.x_u_osc_u132.e_abmgate1_int1 0 0
xu1.u_osc_n16690334 0 0
xu1.x_u_osc_u132.yint2 0 0
xu1.x_u_osc_u132.yint3 0 0
xu1.x_u_osc_u132.e_abmgate2_int1 0 0
xu1.x_u_osc_u133.yint1 0 0
xu1.x_u_osc_u133.e_abmgate1_int1 0 0
xu1.x_u_osc_u133.yint2 0 0
xu1.x_u_osc_u133.yint3 0 0
xu1.x_u_osc_u133.e_abmgate2_int1 0 0
xu1.x_u28.yint 0 0
xu1.x_u28.e_abmgate_int1 0 0
b.xu1.x_u28.be_abmgate#branch 0 1 *
b.xu1.x_u_osc_u133.be_abmgate2#branch 0 1 *
b.xu1.x_u_osc_u133.be_abmgate1#branch 0 0
b.xu1.x_u_osc_u132.be_abmgate2#branch 0 1 *
b.xu1.x_u_osc_u132.be_abmgate1#branch 0 0
b.xu1.x_u_osc_u136.beqb#branch 0 1 *
b.xu1.x_u_osc_u136.x3.be_abmgate2#branch 0 0
b.xu1.x_u_osc_u136.x3.be_abmgate1#branch 0 0
b.xu1.x_u_osc_u136.bgq#branch 0 0
b.xu1.x_u_osc_u136.x2.be_abmgate#branch 0 0
b.xu1.x_u_osc_u136.x1.be_abmgate2#branch 0 1 *
b.xu1.x_u_osc_u136.x1.be_abmgate1#branch 0 0
b.xu1.x_u_osc_u135.be_current#branch 0 1e-05 *
b.xu1.x_u_osc_u134.be_abmgate#branch 0 0
b.xu1.x_u_osc_u131.be_abm#branch 0 0
b.xu1.be_abm6#branch 0 0
b.xu1.x_u25.be_abmgate#branch 0 1 *
b.xu1.x_u15.be_abmgate#branch 0 1 *
b.xu1.be_abm12#branch 0 1e-09 *
b.xu1.x_u27.be_abmgate#branch 0 1 *
b.xu1.x_u26.beqb#branch 0 1 *
b.xu1.x_u26.x3.be_abmgate#branch 0 0
b.xu1.x_u26.bgq#branch 0 0
b.xu1.x_u22.beqb#branch 0 1 *
b.xu1.x_u22.x3.be_abmgate#branch 0 0
b.xu1.x_u22.bgq#branch 0 0
b.xu1.be_abm11#branch 0 5.5e-05 *
b.xu1.x_u4.beout#branch 0 0
b.xu1.x_u4.behys#branch 0 0
b.xu1.x_u21.be_abmgate#branch 0 0
b.xu1.be_abm7#branch 0 0
b.xu1.x_u2_ctrl_u2.beout#branch 0 0
b.xu1.x_u2_ctrl_u2.behys#branch 0 0
b.xu1.x_u2_ctrl_u9.be_abmgate#branch 0 1 *
b.xu1.x_u2_ctrl_u18.be_abmgate#branch 0 0
b.xu1.x_u2_ctrl_u3.beout#branch 0 0
b.xu1.x_u2_ctrl_u3.behys#branch 0 0
b.xu1.x_u2_ctrl_u10.be_abmgate#branch 0 1 *
b.xu1.bg_abmii2#branch 0 0
b.xu1.x_u2.beout#branch 0 0
b.xu1.x_u2.behys#branch 0 0
b.xu1.be_abm3#branch 0 0
b.xu1.be_abm8#branch 0 0
b.xu1.bg_abmii4#branch 0 0
b.xu1.be_abm2#branch 0 1 *
b.xu1.be_abm4#branch 0 0
e.xu1.x_u28.e_abmgate#branch 0 0
e.xu1.x_u_osc_u133.e_abmgate2#branch 0 0
e.xu1.x_u_osc_u133.e_abmgate1#branch 0 0
e.xu1.x_u_osc_u132.e_abmgate2#branch 0 0
e.xu1.x_u_osc_u132.e_abmgate1#branch 0 0
e.xu1.x_u_osc_u136.eqb#branch 0 0
e.xu1.x_u_osc_u136.x3.e_abmgate2#branch 0 0
e.xu1.x_u_osc_u136.x3.e_abmgate1#branch 0 0
e.xu1.x_u_osc_u136.eq#branch 0 0
e.xu1.x_u_osc_u136.x2.e_abmgate#branch 0 0
e.xu1.x_u_osc_u136.x1.e_abmgate2#branch 0 0
e.xu1.x_u_osc_u136.x1.e_abmgate1#branch 0 0
e.xu1.x_u_osc_u135.e_current#branch 0 0
e.xu1.x_u_osc_u134.e_abmgate#branch 0 0
e.xu1.x_u_osc_u131.e_abm#branch 0 0
e.xu1.e_abm6#branch 0 0
e.xu1.x_u25.e_abmgate#branch 0 0
e.xu1.x_u15.e_abmgate#branch 0 0
e.xu1.e_abm12#branch 0 0
e.xu1.x_u27.e_abmgate#branch 0 0
e.xu1.x_u26.eqb#branch 0 0
e.xu1.x_u26.x3.e_abmgate#branch 0 0
e.xu1.x_u26.eq#branch 0 0
e.xu1.x_u22.eqb#branch 0 0
e.xu1.x_u22.x3.e_abmgate#branch 0 0
e.xu1.x_u22.eq#branch 0 0
e.xu1.e_abm11#branch 0 0
e.xu1.x_u4.eout#branch 0 0
e.xu1.x_u4.ehys#branch 0 0
e.xu1.x_u4.ein#branch 0 0
e.xu1.x_u21.e_abmgate#branch 0 0
e.xu1.e_abm7#branch 0 0
e.xu1.x_u2_ctrl_u2.eout#branch 0 0
e.xu1.x_u2_ctrl_u2.ehys#branch 0 0
e.xu1.x_u2_ctrl_u2.ein#branch 0 0
e.xu1.x_u2_ctrl_u9.e_abmgate#branch 0 0
e.xu1.x_u2_ctrl_u18.e_abmgate#branch 0 0
e.xu1.x_u2_ctrl_u3.eout#branch 0 0
e.xu1.x_u2_ctrl_u3.ehys#branch 0 0
e.xu1.x_u2_ctrl_u3.ein#branch 0 0
e.xu1.x_u2_ctrl_u10.e_abmgate#branch 0 0
e.xu1.e_u2_ctrl_e1#branch 0 0
e.xu1.x_u2.eout#branch 0 0
e.xu1.x_u2.ehys#branch 0 0
e.xu1.x_u2.ein#branch 0 0
e.xu1.e_abm3#branch 0 0
e.xu1.e_abm8#branch 0 0
e.xu1.e_abm2#branch 0 0
e.xu1.e_abm4#branch 0 0
v.xu1.x_u_osc_u136.v2#branch 0 0
v.xu1.x_u_osc_u136.v1#branch 0 0
v.xu1.v_u_osc_v45#branch 0 0
v.xu1.v_u_osc_v46#branch 0 0
v.xu1.v_v22#branch 0 0
v.xu1.v_v12#branch 0 0
v.xu1.v_v14#branch 0 0
v.xu1.v_v27#branch 0 0
v.xu1.v_v26#branch 0 0
v.xu1.v_v15#branch 0 0
v.xu1.x_u26.v2#branch 0 0
v.xu1.x_u26.v1#branch 0 0
v.xu1.x_u22.v2#branch 0 0
v.xu1.x_u22.v1#branch 0 0
v.xu1.v_v23#branch 0 0
v.xu1.v_v18#branch 0 0
v.xu1.v_v9#branch 0 0
v.xu1.v_u2_ctrl_v10#branch 0 0
v.xu1.v_u2_ctrl_v9#branch 0 0
v.xu1.v_u2_ctrl_v11#branch 0 0
v.xu1.v_u2_ctrl_v12#branch 0 0
v.xu1.v_v16#branch 0 0
v1#branch 0 0
No. of Data Rows : 0
doAnalyses: iteration limit reached
run simulation(s) aborted
Background thread stopped with timeout = 0
Reset re-loads circuit KiCad schematic
Circuit: KiCad schematic
So... how have I screwed up my design and settings?
