Will this MOSFET buffer work as intended?

Question

I have a circuit whose input is either at the supply voltage or ground. This feeds into a high pass filter with a time constant around \$RC \approx 1\ \text{s}\$. Example input looks like the black line below, while example output is like the red line. In this case the output is inverted, but this is not really important.

The signal source has high output impedance, so I have come up with the MOSFET circuit below (left fragment) which always has a low impedance path to the rail (ground if input is high, supply if input is low). The idea is that the left side of the capacitor will always follow the input signal (only inverted), giving essentially zero output impedance and not loading the RC filter as seen in the right fragment.

My questions are:

• Will this circuit work as intended?
• Is there a name for this simple configuration?
• Is there a better way of doing it?

Answer 1

What you've drawn is essentially this:

^{simulate this circuit – Schematic created using CircuitLab}

I think you have tried to combine a pair of common-source (drain?) MOSFETS to obtain some kind of push-pull stage. That's not a bad idea, but it's badly implemented here.

For starters, M2, a P-channel device is upside down. In this configuration its gate will have to be very negative (way lower than its source, which is at ground potential, 0V) to switch on. Since that never happens, the MOSFET M2 is always off.

Secondly, M1 is configured is common-drain, also known as "source follower". That's OK, in that its source follows gate potential, but it's going to fail in this application because the source is always a couple of volts lower than the gate, not exactly the same.

Lastly, those resistors do play a role when paired with a single common-drain or common-source transistor, but in a push-pull setup they are redundant. The idea is to replace the resistor with another transistor, not supplement it.

Since your input signal is square (digital), and you want a lower impedance copy of it, common-drain arrangements are not very useful here. Perhaps a better solution would be a pair of common-source MOSFETS in a totem-pole configuration. In this way, each transistor is either fully on or fully off, in keeping with the digital nature of the source:

^{simulate this circuit}

Without more information regarding frequency, amplitude, rise/fall times and so on, it's impossible to know if this simple solution will work for you, or even what power supply voltage is required. This particular approach suffers from shoot-through, a condition where during the rise and fall of gate potential, there may be a period of time during which both transistors are conducting, resulting in a potentially large current being drawn from the supply voltage source.

Is there any reason why you can't use an op-amp as a voltage follower, to provide a low-impedance copy of the input? It's dead simple:

^{simulate this circuit}

This solution provides an output impedance very close to zero, although it will be current limited to about 10mA or so. The output will be an almost identical copy of the input, and presents almost no load at all to the input source. Also, it's quite insensitive to power supply voltage, what goes in, comes out. Beware of op-amp limitations such as output voltage range (which always depends on its two power supply potentials).