Grouping MCU pin connections

Question

I'm trying to decide on pin mapping (forgive me if this is the wrong term) for a PIC32MZ1024EFF100, but this isn't something I've ever done before.

There are 32 GPIOs and 8 Analog inputs that need to be connected. I want to ensure they are connected to the optimal pins of the MCU, but I don't know how to tell what is optimal.

For groups of connections that share similar functions, should I:

• Connect them to pins that are physically close to each other?
• Connect them to pins that share the same register inside the PIC?
• Or is there something else I should be considering instead?

Answer 1

In case there are no critical EMC or high speed signal issues, then normally the software engineer is allowed to dictate which pins to use and group them as per how the GPIO peripheral port registers are defined in the MCU. That is, your option "Connect them to pins that share the same register inside the PIC"

If you for example have some 8 bit "port x" register and mean to use 8 pins for a related purposes in software - lets say parallel input from an external 8 bit dip-switch or shift register - then you would use the pins corresponding to "port x", no matter where they happen to be located on the package.

The MCU manufacturer has already made internal EMC considerations regarding analog, digital and clock parts, usually keeping the oscillator pins or timer/PWM pins away from the analog pins etc.

Now in case you have sensitive signals like some high speed bus, high resolution analog signals, bit-banging to/from a RFIC or similar, then the PCB designer should be the one deciding which pins to use and the software designer has to adapt accordingly. Such signals should be given top priority in the PCB layout overall, which normally means keeping the traces as straight and short as possible, avoiding vias if possible etc.

Answer 2

Where you have options, you can give some thought to physical connections if you expect layout to be gnarly, or you can give some thought to logical arrangement if you expect to need to wring the last bit of speed out of the MCU, but often these days it's not so important - we often have luxurious amounts of speed and potential layout density (and you can always go back and revise it later if necessary- non-trivial design is typically iterative).

Generally, I think optimizing the logical connections make more sense even if it's a bit harder on the layout dude (and even if the layout dude happens to be you). Of course there will be exceptions (for example, you might be cramming a chip into a narrow housing and you can't even use some of the pins realistically).

And don't forget to make the schematic easy to read (start with that) and document design decisions, perhaps by separating the pins in blocks into different schematic symbols if there are a plethora of them. That will minimize the potential issues with communicating with the firmware dude (even if that dude happens to be you) and for potential future revisions (you might be surprised by how much gets forgotten in a few short years with many projects inbetween).

Although links to external 'answers' are frowned upon here, I would suggest seeking out the video tutorials of people such as Robert Feranec and Phil Salmony and following many of their recommendations on creating both schematics and layouts. There is far more to this than can be contained in a dozen suitable-length answers here.