Ripple rejection of capacitance multiplier when compared to linear regulators

Question

There are some posts and discussions how a circuit popularly called a “capacitance multiplier” could reduce low frequency ripple noise (at 50/60 Hz or 100/120 Hz) and could perform better than common (jelly bean) series regulators for higher-frequency noise ripple, as 10 kHz to 100 kHz, for instance.

I presented some context and references first, then posted questions interleaved with comments to share my points of interest - in case you see shortfalls in the examples or logic, please help to clarify the matter.

Clarification: I don’t know who named the circuit a ‘capacitance multiplier’ and I agree with Tobalt that such a circuit behaves as a ‘buffered low pass’ that could be nicknamed better (as ‘ripple smoother’, etc.), but that capacitance multiplier is preserved here for its popularity, as other misnomers in electronics - ‘Joule thief’, for instance.

Classic Capacitor Multiplier and Variants:

1. Single-resistor + capacitor on transistor-based capacitance multiplier as seen here and explained by Dave’s EEVBlog here and his video here:

2. Reduced voltage with resistor-divider + capacitor feeding transistor on capacitance multiplier to increase linear operation of the transistor - discussed here and in Elliott Sound Products (ESP here) - both highlighted in yellow:

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Update: The functional improvements of using this resistor are didactically explained by ‘FesZ Electronics’ video here with simulations in LTspice.

3. Reduced voltage with Zener + capacitor feeding transistor - it could be seen either as a capacitance multiplier or as a crude series regulator - as seen here:

The right-side circuit includes some additional diodes for protection of the transistor, sure, as addressed and modeled by Antonio51 here (and in another post, but I could not find the link in this question).

Questions:

1. Why does the capacitance multiplier have a better response ‘filtering’ the higher frequencies from Vin to Vout than a series regulator (at least for LDO as MCP1700 - upper left)?
   See, for example, the screenshots from the above mentioned EEVBlog’s video - showing ripple response at 100 Hz and 10 kHz:

Clarification: the author of that ‘video tutorial’ is also the administrator of EEVBlog and he is the one who compares some ripple features of a low power LDO regulator (as MCP1700) with this capacitance multiplier.

I’m just delivering/sharing the message, from a reputable (for me) source of information.

2. Regarding noise and ripple suppression, is a capacitance multiplier circuit as good as (or better than) common (aka jelly bean) series voltage regulators?
   Please consider not only 100/120 Hz (linear PS) scenario, but also 10 kHz and 100 kHz (SMPS) as “ripple noise” fundamental frequency.

Some datasheets of common LDO regulators as AMS1117 do not post ripple rejection per frequency, but TI’s LDO LM1117 shows these curves:

Moreover, regular series voltage regulators as TI’s LM317 show similar response as ripple rejection of about -60dB (@ 10 kHz) reducing to -40dB (@ 100 kHz), when 5 V is available as voltage differential (Vin-Vout):

On the other hand regarding the capacitance multiplier, the screenshots of that video show an attenuation that is not strongly dependent on the noise frequency - compare the responses at 100 Hz (lower left) and 10 kHz (upper right.)

3. Could the above behavior be seen as “less frequency-dependent” response of the capacitance multiplier and be extended to 100 kHz or more? If not, which would be the limitations expected?
   Wouldn’t it be useful as a kind of ‘power-filter’ (or amplified RC - see screenshot at lower right) to reduce the noise generated by SMPS and ‘ringing glitches’ that some diodes and inductors/transformers could cause?

Update: Regarding high frequency (HF) noise sources and their filtration, caused by SMPS, this FesZ’s video shows both in simulation and in real life how to reduce such noise, but my point here is to understand if the capacitance multiplier would be capable of reducing the HF ripple noise and be less frequency-dependent as illustrated by EEVBlog’s video.

Disclaimer: I know the terminology I used is far from the most adequate one, so I would appreciate hearing any better definitions as answers or comments to explain such phenomena.

4. Could the capacitance multiplier (all 3 variants shown above) be seen as an open-loop circuit of current-amplified ripple suppression?
   If this is unacceptable by any means, could someone elaborate where (and how) this ‘loop’ is ‘closed’?

I see it this way: while not being a voltage regulator, it could be loosely seen as a faster “ripple suppressor”, using the intrinsic RC response polarizing the base of the transistor, while amplifying the output current, due to hFE of the BJT.

Probably a more comprehensive model of a BJT operating at really high frequencies >> 100 kHz and its internal capacitances and inductances could change the response of the component itself (BJT.) I don’t know how this would be modeled and how much this influence would be.
Furthermore, wouldn’t this be worse on a linear regulator with error amplifier, etc., which would be really be operated in a closed-loop layout?

Answer 1

1 - Why the Capacitance Multiplier has a better response ‘filtering’ the higher frequencies

The very low quiescent current of the MCP1700 suggests that \$gain \times bandwidth\$ product is not wonderful. Indeed, at 10 kHz., line regulation sucks...data sheet suggests that output ripple should be about half input ripple.
\$\beta\$ of the capacitor-multiplier at 10 kHz. is pretty-much identical to \$\beta\$ at 100 Hz. Ripple rejection of its RC filter should improve as frequency goes up, at least to a few MHz, where \$\beta\$ starts to fall off.

2 - Regarding noise and ripple suppression can a CM circuit be considered as good as (or better than) common (aka jelly bean) series voltage regulators?

Keep in mind that capacitor-multiplier filtering ripple rejection is dominated by its RC low-pass filter, so low-frequency filtering should be inferior to a properly designed active regulator. Even with \$\beta multiplication\$ a very large RC product is needed to filter low frequency ripple.
As for low-amplitude noise, many transistors (especially the physically-larger ones) have lower intrinsic noise sources than the op-amp-like gain stages inside active regulators...especially if you consider 1/f noise at really-low frequencies.
Trying to filter-out this really-low-frequency noise with a shunt capacitor attached to an active regulator's output is nearly impossible, because output impedance is often a fraction of an ohm. This output-shunt capacitor only starts to be effective when the internal gain stage of the active regulator drops-off at high frequency (perhaps above 10 kHz).
Dave mentions in his blog that ripple rejection of capacitor-multiplier circuit can be quite good, but stresses that load regulation is terrible when compared with an active regulator like LM317.
As for switching regulators, consider noise at frequencies not related to switching frequency and its harmonics. Noise floor performance in this context can be as good as linear regulators.

3 - Could the above behavior be seen as “less frequency-dependent” response of the CM and be extended to 100 KHz or more? If not, which would be the limitations expected?

Above 100kHz, a shunt capacitor adjacent to the load should be considered superior. Inductance of conductor paths between regulator and load (and back) become significant.
As for the capacitor-multiplier circuit, equivalent-series-resistance of the (electrolytic) capacitor becomes significant at some point.
Dave also misses the nasty tendency of the capacitor-multiplier circuit to oscillate at very high (VHF) or ultra-high (UHF) frequencies. Take a closer look at OP's upper-right photo of Dave's test circuit. It shows a fuzz on top of output waveform. This fuzz could possibly be oscillations at hundreds of MHz. Tiny inductances in the base and/or emitter have not been accounted for that cause oscillation. Oscillation amplitude is often small and easy to miss. In actual use, I have often found this simple capacitor-multiplier oscillating - but a good quality 'scope doesn't show it. Ferrite beads on base and/or emitter might be needed.

4 - Could the CM (all 3 variants shown above) be seen as an Open-loop circuit of current-amplified ripple suppression?

Be careful here - you're assuming linear circuit operation. Consider that a down-stream capacitor often exists. This capacitor-multiplier circuit can only source current, and cannot sink current. A non-linear load can suddenly disappear, or even rise in voltage momentarily. Transistor current falls to zero.
Many active regulators suffer the same problem, but since their load regulation is often far superior to capacitor-multiplier circuit, the consequences are less-dire.

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An alternative noise-reducing post-regulator circuit:
Charles Wenzel offered this feed-forward noise cancel circuit. Like a capacitor-multiplier, load regulation is not great. Unlike a capacitor-multiplier, AC noise is amplified, inverted, and current is added to output so that very low-amplitude noise is attenuated. It can improve noise performance of many linear regulators.

Answer 2

Why does the capacitance multiplier have a better response ‘filtering’ the higher frequencies from Vin to Vout than a series regulator

There is nothing intrinsic about a linear regulator that gives it poor ripple rejection. In fact many linear regulators have excellent ripple rejection, at both low and high frequecies.

What is intrinsic to linear regulators, and indeed to all engineered products, is that their design involves trade-offs.

A capacitance multiplier trades voltage headroom for ripple rejection. The ripple rejection is not "free".

If a given linear regulator has insufficient ripple rejection at a frequency of importance, AND one has sufficient voltage head-room to play with, then one can cascade a capacitance multiplier with a linear regulator, OR one can choose a different linear regulator.

On the other hand, if one's objective is to, say, provide a regulated 3.3 volt output from a Li-ion battery, that might need to operate at a terminal voltage as low as 3.6 or 3.7 V, one neither NEEDS special ripple rejection, nor can one AFFORD (in terms of loss of headroom) the superfluous ripple rejection.

In short, low drop-out may be the primary design objective of a linear regulator, or high ripple rejection may be the primary design objective, or their may be some other primary design objectives (or some compromise) but it all boils down to design objectives.

Answer 3

To begin with, the capacitance multiplier is a block that, typically, is added on top of a voltage regulator to aid in ripple filtering.

As already pointed out by others, even by Dave Jones himself, the capacitance multiplier is simply meant to filter out high-frequency noise more effectively, while the voltage regulator's job is to keep the output voltage constant no matter the variations at \$V_{in}\$.

I'm not going to regurgitate what others have already pointed out, so I'm going to go with some of the other comments you made on a previous answer.

One of the reasons why ripple regulation could be disappointing in LDO in contrast to a capacitance multiplier is, that the typical LDO topology has roughly 3 dominant poles (error amplifier input, pass element and , which is a nightmare to compensate on in a feedback system. This will cause the LDO to be "crippled" in the sense that some aspects of it have to be given up in order to have stability and a usable range of bypass-capacitor/ESR combination that users can implement in their designs.

Taken from Ricón-Mora's Current-Efficient, Low-Voltage, Low-Dropout regulators

In addition to that, a capacitance multiplier only filters out ripple without any regards to what DC input voltage it receives. Therefore, it is not a fair comparison to say that ripple rejection is worse in an LDO than in a capacitor "multiplier" without considering the rest of the LDO's job.

This brings me to the early reason for your question: is the capacitor multiplier an open-loop or a closed-loop type of system? I see your point of it being "open-loop" since it doesn't regulate voltage at all. However, since that's not its purpose, calling it an open-loop regulator seems a bit out-of-place.

I call it a closed-loop system because it's using an emitter follower, which uses series (input) - shunt (output) feedback.

How is, then, the emitter follower a closed-loop system? An emitter-follower can be modeled as negative feedback circuit because an increased in emitter voltage will lead to a decreased Vbe voltage, which in turn reduces the current through the transistor.

The voltage gain of a common-collector is given by (Assuming the load is $R_L$): $$ A_v = \frac{g_m R_L}{g_m R_L + 1} $$

You can consider the "open-loop" gain to be \$g_m R_L\$. However, as you can probably imagine, the \$g_m\$ is not constant along frequency, it will drop at higher frequencies.

By the same token, you'll find that the \$Z_{out}\$ of the emitter follower is scaled down by a \$(1+g_m R_L)\$ factor. It will go up with frequency.

You can do the math to prove to yourself that this is the case with the capacitance multiplier, too. This link: TF, Zin, Zout Capacitance multiplier derivation has more information about how to derive the expressions relevant to that circuit. You'll see that the output impedance are scaled down by beta (which equals \$g_mr_{\pi}\$).

IMHO, the most elegant way to remember this is to think of the nullor voltage follower implementation:

The emitter follower:

The op-amp voltage buffer:

(They're all, obviously, AC/small-signal schematic representations only, hence the grounding of the op-amp power supplies.)

In this way, it's easier to remember that, just as a the op-amp voltage buffer, the emitter follower also uses shunt feedback at the output. Shunt feedback will make your closed-loop output impedance very low (but not well-defined, to do so you need at least 2 loops at the output, but that's more complicated).

The output impedance will very low at DC, but it will grow as the loop gain drops at high frequencies => inductive-like behavior at the output. The voltage buffer will suffer from the same, only that its closed-loop output impedance will be much lower than the emitter follower due to huge loop gain available at DC.

From remembering this, you could've foreseen that, at least in theory, you could replace the emitter follower by an op-amp voltage buffer (of course, you have to add another resistor from input to output because the op-amp doesn't lend itself to sense current in series at its output; it only has one node, not 2).

And that is exactly the kind of circuit that Dave shows towards the end of the video. He argues, though, that it's probably not so good to use because of the current-handling and stability considerations of an op-amp, which are, usually, more restrictive than a single transistor. I agree with that.