Common Source NFET--dropping gate drive causes negative pulse on drain

Question

Hi folks, I'm simulating this very simple common source circuit with an NFET, with a pulse input on the gate input. On the falling edge of the gate voltage, I see a small negative output excursion on the drain terminal of the FET.

I'm wondering why this is occurring.

The green plot is the drain voltage, and you can clearly see the negative excursion right after the gate voltage goes down.

Answer 1

There is drain-gate capacitance (also called reverse transfer capacitance) and your transition is fairly fast (3.3V in 10ns).

Doesn't matter with 22kΩ load, but note that 3.3V is not really enough gate drive for that part if you want very low Rds(on).

If you reduce the drain resistor to (say) 100Ω the negative-going bit should largely or entirely disappear.