Some background: I have a little hobby project running that basically interfaces a 64 pin ARM mcu (the STM32F405RGT6) to a stereo codec (a TI PCM3010) via I2S interface. I'm deriving the master clock for the I2S bus from the MCU (the stm32f4 series apparently has a PLL for this purpose), which runs at 12.288 MHz (256 times the sampling frequency, which in this case is 48kHz). The bit clock and respective data in/data out lines run at approximately 3MHz. I'm currently looking at routing the design on a 2 layer board, since it doesn't really have a huge amount of I/O. So far I've been able to locate the codec literally right next to the MCU, so that trace lengths to respective pins are 3 to 13mm in length (and as a plus, the analog/digital halves are nicely segmented). The ground plane is unbroken, except where I have to use a via for the data out line.
Now for the actual question; is it even required to terminate transmission lines under a certain length? I've seen in some literature that this is case (as in you don't have to terminate anything), but why is this exactly? I know it really depends on the edge rate (and source/destination/trace impedance), but would I gain any benefits by doing it anyway? Due to the layout of the codec chip, it would be possible to series terminate the lines, but really only by moving it further away, and by introducing more vias and broken ground planes into the equation. I realize this is a sort of low speed/edge rate design and I could get away with routing the board with my eyes closed, but I'd actually like to design something properly for once!