Current mode control vs Voltage mode control

Question

I am confused about why we always make the outer (slower) loop a voltage control loop and the inner (faster) loop a current control loop in switched-mode power supplies? I read these links, but they did not seem to explain this. It seems to me that the only requirement is that the inner loop have higher bandwidth (faster response) than the outer, and that makes sense, otherwise we would render the inner loop redundant if it was opposite.

I don't understand why the inner loop is always a current control loop? In one answer, it was mentioned that the dynamics of the plant is such that the input current reacts faster, so measuring the inductor current (= input current, say in a boost converter) is faster than waiting for changes in the load voltage.

But this is only for boost and boost-derived converters. What about other types?

Links I referred to

SMPS : Average Current Control Vs Peak Current Control

Why is current controlled feedback faster than voltage controlled feedback in PWM controllers?

Answer 1

Update: 9 Oct 2024. Updated: Oct 2024

Current feedback has a great advantage because the external voltage control sets a threshold, and once that threshold is hit, the internal current loop steps in to control current spikes in the switch or primary winding.

I assume at steady-state the input current is proportional to the output current, and any sudden change in the output current causes the primary winding current to change too. The current mode PWM responds with proportioned feedback to that shift within one cycle, thus faster than voltage feedback.

This means the external voltage loop can work at a slower pace within many pulse cycles, to attenuate ripple, without causing voltage oscillation issues, while the converter reacts instantly to any output current changes.

I am aware this contradicts expert advisor @verbalkint and current feedback ;) to another old similar thread.

          - fin -

Conclusion: Current feedback is used because it is PROPORTIONAL feedback, which means it is ideal for basic servo stability. It anticipates voltage error from directly sensing load changes, which directly causes load regulation voltage error.

All analog negative feedback control systems (PLLs, SMPS regulators, etc) which I will call servos for some parameters are often based on 2nd order or higher differential equations. But then each isolated order adds 90 deg of phase shift and anything more than 180 deg becomes an unstable positive feedback loop. Compensation networks are used to advance this phase like a partial differentiator or series RC in the feedback and may add an integrator for null steady-state error with a compromise to phase margin.

Thus the basic challenge is to reduce the ripple error below the design spec such as =1% ripple max, with a minimal overshoot on step load response and adequate settling time. These are the three basic behaviours in analog specs for all servos. Let's talk about current feedback in SMPS.

The servo loop ends up between a 1st and 2nd order response at unity loop gain or say 60 degrees phase margin as ideal and < 30 deg and inadequate for most applications. Proportional current feedback is "zero order" feedback. Although, this is not always the target for every servo loop with variations like pulse skipping, soft start, dual bandwidth, zero-valley switching, synchronous switching, feed-forward load prediction, mutual coupling of parallel outputs and high efficiency add more complexity with better performance, possibly some tradeoffs.

While an ideal stable gain is zero order current feedback with 1st order voltage feedback, other compensation is added to partially differentiate with RC to predict current changes also includes pumped forward current noise, so it can only slightly improve load-regulated noise with a low gain ratio.

However, voltage drop in either buck or boost across an inductor is a 1st order response for a repetitive waveform with harmonics and according to Ohm's Law, you can alter V=I*R and R to mean Inductor impedance over a repetitive cycle.

Since SMPS pulse current towards the output with switches, if you attenuated 100% of the ripple, you would have zero feedback, it would not be able to regulate AC step/ripple error and only regulate DC, which we say is unstable (like driving with very slow reactions), so you must have some voltage ripple to regulate error and be "stable". Often 1% is a common tradeoff yet many great supplies found on MOBO's for the CPU are better and need low noise for the CPU logic in order to raise the SNR of logic signals so the data error rate is much longer than your lifetime in theory or the life of the weakest link. Although 1% ripple alone means SNR=40 is not the only source of noise. Those who recall what load regulation and switched CMOS capacitance induced current noise with Shannon/Hartley Theorems on SNR vs BER will understand. It means a very small but non-zero theoretical error rate is needed for CPUs which have their own dedicated MOBO DCDC converters near the IC to be error-free in their lifetime.

A linear regulator is like a PROPORTIONAL Op-Amp circuit and has very low output impedance from high error gain negative feedback which is the critical spec that defines Load regulation error for step loads. Except the low internal resistance from BW limited negative feedback and the load cap buffers the regulator but adds an order to the control loop with this low pass filter. FET-based LDO's with very high loop gain are more critical than BJT types with lower gain and the small dropout demands the ESR range to be not too low for phase margin reasons or high for step load error reduction.

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I apologize if my terms are awkward or incorrect. I will approve any improvements. Maybe I should have asked ChatGPT. ;) lol

Answer 2

Assuming a basic boost or buck configuration, voltage-switched inverter, and L-C lowpass filter:

Simply put, the state variable of the inductor is its current, and the state variable of the capacitor is its voltage.

If it were a current-switched inverter, the first filter component would be a capacitor, and use a voltage error amp. A voltage regulator would end there (albeit having pretty high ripple, but a CLC filter would clean up nicely). Current sources are less common in nature, so this doesn't turn up too often, but there are applications from time to time.

For a general perspective, we can put the state of each component in the system, into a list -- the state vector. Then, instead of nodal analysis producing a matrix relating component voltages and currents, we have a state transition matrix, which describes the same sort of thing but in terms of node voltages/branch currents and their derivatives. This is known as state space representation. Much as nodal analysis consists of inverting the matrix to solve for voltages and currents, we solve the system of differential equations by exponentiating the state matrix (which sounds terrifically esoteric, but isn't actually all that bad, just numerically tiresome -- in other words, let a computer handle it).

When we design a control system, we want to have control of as many state variables as possible, to minimize phase shift/delay and control error through the system; the cascaded error amp system achieves this for the LC filter case. This is quite apparent when comparing the control dominant pole to the LC filter: a voltage mode control must come in below \$\omega_0 = \frac{1}{\sqrt{LC}}\$ to avoid the large phase shift beyond this point, but a current-mode control can cut above this point.