Generating 48kHz clock for DSP

Question

I'm working on a Microblaze-based system. I'm using FSL to shuttle data directly from an AC'97 controller core to my custom DSP core. The FSL buses are clocked at the 125MHz system clock. The DSP components have been designed with a 48kHz clock in mind (the codec sampling rate).

How do I go about clocking the samples through the DSP components at 48kHz?

FSL bus is essentially a FIFO, that signals when data is available for the slave to read. Through some experimentation, I'm seeing samples arrive at approximately 48 kHz (I was using a timer interrupt in the uBlaze to monitor this, hence the "approximately"). Is there any way I can generate a sane "clock" from this fact, and also allow XST to understand the timing requirements of what I'm doing?

Answer 1

Clock the DSP at 125MHz, but apply a "clock enable" signal to it that is pulsed active every 2604 clocks @ 125MHz; that will give you a DSP rate of 48,003Hz - well within the error you can expect on the original clock.

Answer 2

As markt suggested, the solution is clock gating.

I have placed all of my project code on GitHub. You can see where I handle the FSL bus transactions here.

The entire design remains in the 125 MHz system clock domain, but a clock enable signal is used throughout the DSPs. Since this happens every sample, I named this signal samp_ena. Sample usage:

process (sys_clk) is
begin
   if rising_edge(sys_clk) then
      if samp_ena = '1' then
         -- Register new sample
      end if;
   end if;
end process;

I'm generating this samp_ena signal in my FSL transaction state machine. An example:

case fsl_state is
   -- ...
   when FSL_SREAD =>
      if (FSL_S_Exists = '1') then
         new_sample <= FS_S_Data;
         samp_ena <= '1';
         fsl_state <= FSL_MWRITE;
      end if;
   -- ...
end case;

-- Pulse samp_ena for one sys_clk only
if (samp_ena = '1') then
   samp_ena <= '0';
end if;