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I need to create a dynamic flip flop like this:

flipflop

In integrated circuit technology, at mask layout level. I then want to create an 8bit register, using 8 of these flip flops, with a common CLK signal. So that register will memorize an 8-bit vector on an positive edge of CLK, something like this:

register

So I created the flipflop in IC like this: icff

But it seems somewhat ugly, and I don't know exactly how I'd fit it in my 8bit register. Do you have any ideas how I'd go about doing that? Maybe change the layout, or make it smaller? I used minimal sizes for the NMOS transistors, and optimal PMOS sizes for having symmetrical edges 1->0 and 0->1 (Width of PMOS/NMOS = 2.4)

Any ideas? thanks!

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  • \$\begingroup\$ Without feedback, it isn't a flip-flop; at best it's a delay line. And since your actual question is about aesthetics, answers are going to be primarily opinion-based, making it rather unsuitable for this site. (One suggestion I would have would be to share the P-well between adjacent pairs of bits.) \$\endgroup\$ – Dave Tweed Mar 15 '14 at 15:35
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    \$\begingroup\$ @DaveTweed it almost certainly is a D FF or D latch, which ever you want to call it. Aesthetics can actually map to easily quantifiable terms like signal flow and parasitics. And most importantly, while unlabelled, the P-Well is indeed already shared. PWell is commonly not draw anyways as it is default, one has to often block PWell if you want no well implants (on epi) or it is just the substrate. \$\endgroup\$ – placeholder Mar 15 '14 at 15:41
  • \$\begingroup\$ @placeholder: Well, it's been 30+ years since I was actively involved in chip design at this level, so perhaps I'm using terms differently than you are. To me, "dynamic logic" implies that the clock runs continuously. A "latch" or "flip-flop" is a device that will hold its state indefinitely, which isn't possible without feedback. (It turns out that the OP probably just needs a delay line for his FIR filter.) \$\endgroup\$ – Dave Tweed Mar 15 '14 at 21:59
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It's obviously just a start, but if that is your first layout attempt it isn't so bad. You're obviously missing lots of details like bulk contacts, labels for your rails, labels on your intermediate signals (Inp) and ports so you can instantiate this at a higher level. I would use a transmission gate rather than just a NMOS pass gate into the bus holder circuits. It gives a larger control range and balances out the leakage current into the storage node(s) (gate capacitance of the inverter). It might be easier to put a simple feedback inverter (bigger L to be weaker drive) to have an actual static bus holder like design to be more robust.

In general a dynamic circuit is something should be clocked for most of it's oppertion, it sounds like you're looking at more of a latching operation so I'd recommend going to a static configuration.

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  • \$\begingroup\$ By bulk contacts you mean substrate contacts? And yeah, didn't add labels yet, coz I didn't simulate it yet, still working on design :) This register is going to be a part of a FIR filter, so I was advised to use dynamic FFs for some reason :) Do you have any advice regarding the layout design, in order to easily link 8 of these FFs together, with a common CLK? Should I put them one above the other, or on the side? Where do you suggest I put the buffers to drive those CLK lines? Thanks! :) \$\endgroup\$ – Vidak Mar 15 '14 at 18:08

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