Both setups may work. Which is better is governed by capacitor values, their ESLs and the power delivery network downstream.
In the left-hand setup, the PDN should provide low impedance path at lower frequencies. This is the requirement for this setup to work.
The potential advantage of paralleling two capacitors is lower power impedance in a broader range (assuming 0.1 uF and 10 uF cover different frequency ranges). As for the notorious anti-resonance of the two capacitors - look at impedance frequency curves. The situation when it happens is when one capacitor is still capacitor and another one is an inductor. This should not be the case. So, the answer provided by Spehro makes sense as well.
As for the right setup, it may work also. But note that C1 is the only one to provide power when the bead is closed - so its responsibility is huge. The left larger capacitor may not be needed in close proximity (as assumed by the pic I guess). If the bead closes early (say in units of MHz or tens of MHz), then it should provide low impedance path at kHz (or units of MHz) frequencies where location requirements are relaxed (as light wavelength is on the order of tens of meters at these frequencies). But it depends.
Below are some general considerations re ferrite beads that might be interesting.
Consider for simplicity the setup with only one capacitor. The main purpose of the second capacitor in the pi setup is to provide low impedance to power at lower frequencies:
Capacitance value required
Murata's application note, page 11, says
I guess, the way the derived the formula was as follows. They assumed reactance of the inductor and the capacitor equal (Lw=1/cw), calculated frequency, expressed Zt in terms of frequency to get the equation. This is not correct in general. First, impedance of a capacitor in general does not equal to 1/Cw, especially at high frequencies where ESL dominates. Second, the impedance of the capacitor should be much (orders of magnitude) smaller than the impedance of the inductor, not just smaller (2x or 3x times smaller wouldn't work).
The correct way would be to compare the impedance-frequency curves of the capacitor and inductor (accounting for the DC bias used, ideally) and to make sure the impedance of the capacitor is much smaller then the impedance of the inductor where it needs to be. It is not simply some capacitance value needed. The required value of the capacitor's impedance (at some frequency) may be calculated as deltaV/current, where deltaV is an allowable voltage fluctuation and current is the current amplitude at this frequency.
Operation of a ferrite bead
Let's consider as an example this bead BLM03AX241SN1:
Typical impedance of a power delivery network (PDN) seen in PCB with power/ground planes is from hundreds mOhm to units of Ohms. So the bead is effectively an open connection (resistance ~100 Ohm) starting from several MHz.
It means the whole PDN is cut off from the chip. All hope is for the capacitor. Thus, the importance of the capacitor, if a ferrite bead is used, becomes paramount. Unproperly chosen capacitor would make the chip inoperable. Badly selected bypass cap wouldn't be such a problem if a bead is not used due to action of other capacitors (in parallel).
IR drop at low frequencies
Ferrite beads for power filtering are usually designed as low-q inductors to prevent parasitic resonance. So, DC resistance of ferrite beads is made intentionally high. Often it is about 500 mOhm or even several Ohms. Select a bead with an appropriate DC resistance (there are special series for power lines with relatively low DC resistance). Make sure you can tolerate IR drop given your DC current (say, 10 mA current at 500 mOhm produce 5 mV drop).
High frequencies (>500 MHz)
Inductor is open. Impedance of the capacitor would likely be relatively high (~500 mOhm or even Ohms).
W/o the bead, other capacitors on the board, as well as, planar capacitance of the power planes work for us. And they are all in parallel to the bypass capacitor decreasing PDN impedance. Yes, other capacitors may be located far away, but the planar inductance of the power planes is also very small (current is less concentrated than when flowing in a trace). So, they all have some positive input, despite inductance on the way to them.
This is the reason, ferrite beads are not recommended in high-frequency, high-current circuits (e.g. digital processors), because every hundred mOhm of additional PDN impedance may be critical.
A ferrite bead may be useful in effectively blocking external noise (or vice versa, noise from the chip) withing some frequency range, while providing a DC connection (to charge the bypass cap). A bead may have substantial DC resistance producing DC voltage drop. A bead increases overall PDN impedance (I guess, at all frequencies), which might be unwelcome at high frequencies, where capacitors stop working well. Choice of the bypass cap becomes paramount. Always use impedance-frequency curves for both capacitor and the inductor (not just plain values of L and C).