# Using 16bit SDRAM with 8bit bus?

I have a design with an 8bit SDRAM which I want to replace with a 16bit one,the problem is I don't have much pins left to connect all 16bit data bus, is it possible to access the whole memory using an 8bit data bus ?

The ram (IS42S16800E) is organized as 4096 rows x512 columns x16 bits per bank, using 9 bits column, I'm only able to access half the ram, this is acceptable if I have to, however, I tried using 10 bits for column address, and it worked, ran a memory test and I can read/write to every location, but I'm not sure how/why this works, if I understand correctly, it should only use 9 bits for the column address ? so does this depend on the organization of this specific ram ? or is this how all SDRAM work internally ?

Update:

I fixed my ram test (Thanks Dave Tweed) and this time it fails, writing to address base+0 overlaps with base+512 which means the 10th bit is ignored and it wraps around to 0. If I use 9 bits for the column address I can still access half the ram.

Here's my ram test:

uint8_t pattern = 0xAA;
uint8_t antipattern = 0x55;
uint32_t mem_size = (16*1024*1024);
uint8_t * const mem_base = (uint8_t*)0xC0000000;

/* Test data bus */
for (uint8_t i=1; i; i<<=1) {
*mem_base = i;
if (*mem_base != i) {
BREAK();
}
}

for (uint32_t i=1; i<mem_size; i<<=1) {
mem_base[i] = pattern;
if (mem_base[i] != pattern) {
BREAK();
}
}

/* Check for aliasing (overlaping addresses) */
mem_base[0] = antipattern;
for (uint32_t i=1; i<mem_size; i<<=1) {
if (mem_base[i] != pattern) {
BREAK();
}
}

/* Test all ram locations */
for (uint32_t i=0; i<mem_size; i++) {
mem_base[i] = pattern;
if (mem_base[i] != pattern) {
BREAK();
}
}

• Where did you connect the 10th column line? Jul 23, 2014 at 3:33
• @IgnacioVazquez-Abrams It was already connected, I was using 12 lines for the address, the old SDRAM had 12bit row/10bit column
– mux
Jul 23, 2014 at 3:38
• From the datasheet: "Each [...] bank is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits." - You may be accessing the 16-bit part byte-wise here. Jul 23, 2014 at 9:17
• @HannoBinder I think that refers to the second sdram (IS42S81600E) and doesn't mean you can use the 16bit ram with 8 or 16 bit bus, not sure though.
– mux
Jul 23, 2014 at 9:31
• I'm suspicious of your memory test. Being able to read/write every location does not tell you whether certain pairs of addresses are "aliases" of each other -- you need to explicitly check for that. Did you? Jul 23, 2014 at 11:40

If you have a device which puts out 16 bits, and you want to use all of its storage, then in theory what you can is:

• in the reading direction, take the 16 bit output obtained from your address lines A1..AN and pass it through a bank of 2x1 multiplexers, to go from 16 to 8 lines. Your A0 line to drive these multiplexers, so that in effect your A0 line selects which of the two 8 bit halves of the 16 bits are passed to your data bus.

• in the writing direction, you need some buffers which drive each of your 8 lines to one of two possible data pins on the ROM based on address A0.

These two directions can be combined into one using bidirectional multiplexers. For instance, the ON Semiconductor 74FST3257 mux/demux/bus switch provides four 2x1 bidirectional muxes. With a pair of these, you could route 8 points on one side into a choice of two different sets of 8 points on the opposite side, based on the A0 line.

This is complicated enough that it should send you looking for an 8 bit memory part in the first place.

• I have an 8bit part, and it's available so far, I'm just worried it might be getting obsolete. Can I still access half of the 16-bit part ?
– mux
Jul 23, 2014 at 21:08

4096 rows is 12 bits of address space, 512 columns is 9 bits of address space, and 4 banks is 2 bits of address space so, added all up, that's 23 bits, which is 8 388 608 addresses.

The data sheet describes the IS42S16800E as an 8 meg X 16 RAM, so with your 9 bits of column addresses you should be able to access the entire array.

• I think you misunderstood the question. The poster tried using only an 8-bit wide interface with a 10th column address bit and it worked (on a 16-bit-wide DRAM), providing access to all the memory. With a x16 DRAM and only 8 data lines, 8 bits per beat should be unconnected.(If the DRAM was the x8 version of the part, that would be normal, but it seems very strange [to me in my ignorance] for a x16 version.) Jul 23, 2014 at 9:07
• @PaulA.Clayton that's right, the address is not the problem, I only have 8bit data bus.
– mux
Jul 23, 2014 at 9:29

Not quite sure what the problem is? I will just quote the parts from the datasheet that mention/explain the behavior:

Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits.

Physical size of the RAM is fixed, so if your data is half the size you can store twice as much - or to be more accurate: You can store twice as many 8-bit words as you can store 16-bit words.

Inputs A0-A9 (x8); A0-A8 (x16) provides the starting column location.

Which means you use 10 address pins in 8-bit mode (x8) and 9 address pins in 16-bit mode (x16). So what you tried is actually defined in the datasheet and absolutely fine.

Some SDRAMs have the option to work in a 8-bit or 16-bit mode which means for those devices you can always use the full RAM. Other SDRAMs don't have that option and if you use them with a 8-bit databus you are not using the full memory. I guess it depends on how exactly their internal address decoders work.

• I thought that too, but actually I think it was my memory test.
– mux
Jul 23, 2014 at 21:17