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This is a LabVIEW (Software) FPGA (Hardware) question so I don't know whether I should post here or on Stack Overflow.

I have a USRP-2953R and I want to achieve a very simple project. I want to read a signal from RF0/RX1 and output it to RF1/TX1 using the FPGA (not forwarding anything to the host). The signal is centered at 5.9GHz with 10MHz of bandwidth. Is that feasible? What should my approach be?

I have tried different modifications to the "Simple NI-USRP Streaming" project that comes with LabVIEW 2013, but I haven't successfully outputted anything. I'm using LabVIEW 2013 SP1 and I am able to compile and execute code successfully on the USRP FPGA. It simply doesn't do what I want it to do.

Any help would be greatly appreciated.

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  • \$\begingroup\$ This is not an FPGA question, it is a NI and USRP question, it is a SW issue and not an FPGA issue at all. \$\endgroup\$
    – FarhadA
    Commented Nov 6, 2014 at 20:32

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I'm not familiar with that bit of kit (though it looks really tasty and I wish I had one), but I'd suggest breaking it down into steps and confirm each one.

First just try and receive a signal without forwarding it - make sure that side of it is working fine and your receiver configuration / code is correct.

When you have confirmed reception, create a basic transmit bit of code. Even if it's just transmitting a set sequence of digits or something so you can confirm you're configuring the transmitter correctly.

Then finally weld the two together - feed the output of the receiver into the input of the transmitter.

It certainly looks like what you want to do should be perfectly feasible using that device.

Be warned though that the signals must be separate - i.e., contained within a separate medium, like coaxial cable. Wireless transmission would just cause interference between what is transmitted and what is received, basically creating feedback between the two - unless you transmitted on a different carrier frequency to the receiver...

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  • \$\begingroup\$ Just what I have been trying to do. It is just so annoying that the compilation of the FPGA bitfile takes several hours on a compile cluster =S \$\endgroup\$
    – dimme
    Commented Nov 6, 2014 at 9:03
  • \$\begingroup\$ @Dimme - yes, LabviewFPGA is dreadfully painful like that. Hassle them to provide a decent simulation environment for all their FPGA-only blocks (like I did, to no perceptible effect AFAICT...) \$\endgroup\$ Commented Nov 6, 2014 at 20:38

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