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I am designing a linear voltage regulator for 5V (from 30V) at 10mA for a low cost application. Everything works out so far, but I need around 10ms hold-up time in case of an input voltage failure. All the hold-up energy has to be provided by the 5V output capacitor as I cannot use a decoupled input capacitor.

With the help of an LTSpice simulation model I found out that I need around 44μF to provide around 2.7V (which is sufficient) at the end of the 10ms interval. Of course, these results assume ideal capacitors and in this application electrolytic caps would be close enough to ideal.

However, I would prefer to use MLCCs to save a few cents but unfortunately these are not ideal. Their capacitance changes by a large amount if a voltage close to the rated voltage is applied. The measurements regarding this I have seen so far refer to the small signal capacitance under DC bias and I suspect that I cannot use this figures in this application. In fact, in this application there is some kind of DC bias that decreases in an interval of 10ms.

Does the capacitance "recover" during this decrease, even if there is no energy supplied externally? Are there any guidelines how to calculate the discharge to obtain a hold-up time figure?

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  • \$\begingroup\$ @mkeith As I said, I really cannot use a diode-decoupled input capacitor. The reasons for this are complicated and actually do not have any impact on the question. Are you sure about the cost? According to the prices I have, 2x22μF, X5R, 6.3V, cost me around 2.6 cents and 47μF, aluminum, SMT, are slightly under 4.5 cents. The 10V X5R you suggested seem to be more expensive, though, but I do have only "catalog" prices for these. \$\endgroup\$
    – realtime
    Commented Nov 26, 2014 at 4:03
  • \$\begingroup\$ Digikey is what I meant with catalog prices. These might be a pointer to what is cheap and what is expensive. The prices mentioned above are based on high-volume quotes from distributors where essential quality and availability criteria have already been sorted out. Regarding the SMT electrolytic caps I think that there is a minimum price due to the complex packaging that has to withstand the oven cycle and due to the embossed plastic tape. Ceramics do not have these constraints. Finally, even for a decoupled input cap, the hold-up time would still need to be calculated, so what's the point? \$\endgroup\$
    – realtime
    Commented Nov 26, 2014 at 9:22

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I think that the hold time for the MLCC can be calculated numerically as in the following example. The total charge in a linear capacitor Q is C times V. But MLCC is not a linear capacitor and therefore Q=f(V) (some function that we will assume known now).

At time 0, let be V=5V. At this voltage Q0=f(5)=240 uC.

After some unknown small time step, the voltage dropped to 4.9 V. The charge in the capacitor is now Q1=f(4.9)=237.65 uC. (for example).

Assuming a constant current sink I of 10 mA and remembering that I·(delta time)=delta Q. We can calculate delta time=(240-237.65 uC)/(10 mA)=0.235 ms. The first time step took 0.235 ms.

After the following time step, the voltage dropped to 4.8 V. The new charge will be Q2=f(4.8)=235.2 uC. This time step is then (237.65-235.2)/10 mA=0.245 ms.

If this is continued until the voltage arrived to the minimum allowable voltage for your circuit, you only need to add all the time steps to get the hold time.

I chose voltage steps of 0.1 V, but values smaller or bigger can be chosen to get more or less accuracy in the final result. The problem remains to find function f(V).

The capacitance values from the "Capacitance vs DC Bias" graph in the datasheet gives the the relationship between Delta_Q and Delta_V at every DC bias voltage; i.e. it gives the capacitance seen by a small signal.

I think that a good approximation of f(V) could be obtained doing Integral(from 0 to V, of C(V')·dV'). Where C(V') is read from the "Capacitance vs DC Bias" graph.

Finally there is a FAQ from Murata http://www.murata.com/en-global/support/faqs/products/capacitor/mlcc/char/… where the physics behind the capacitance change are explained:

Without a DC voltage, spontaneous polarization can happen freely. However, when a DC voltage is externally applied, spontaneous polarization is tied to the direction of the electric field in the dielectric, and independent reversal of spontaneous polarization is inhibited. As a result, the capacitance becomes lower than before applying the bias.

This explanation would also apply to decreasing DC voltages. If DC voltage slowly decreases (during capacitor discharge) the polarization won't be tied to a particular direction and then the capacitance will increase.

The calculation of the hold-up time, using this method, can be done rather easily with Excel. I attach a worksheet with real datasheet data for a given 47 uF MLCC capacitor and the necessary calculations: Hold-up time comparison betwween given 47 uF MLCC capacitor and a 40 uF linear one

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    \$\begingroup\$ That would be a way to calculate it, but does reality actually behave this way, i.e. is there any capacity "recovery" during discharge? The capacity specifications in the datasheet you refer to are small-signal measurements. Can these really be applied in this context? \$\endgroup\$
    – realtime
    Commented Nov 26, 2014 at 4:07
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    \$\begingroup\$ @mkeith "Just go measure" would be the way to go for a hobbyist. In a professional environment, these measurements for qualifying a part outside its (obvious) specification and without theoretical background data can easily eat up a complete day's worth of work, not to speak of the accompanying paperwork. \$\endgroup\$
    – realtime
    Commented Nov 26, 2014 at 9:49
  • \$\begingroup\$ Realtime, yes I think those capacity specifications for small AC at given DC bias can be used because it gives us, after all, the relationship between Delta_Q and Delta_V at this particular DC bias voltage. In the other hand, if there is no some kind of memory effect that I'm unaware of, the capacity would increase during discharge the same way it decreases during charge, without hysteresis. \$\endgroup\$
    – Roger C.
    Commented Nov 26, 2014 at 9:52
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    \$\begingroup\$ @realtime, I've found a FAQ from Murata murata.com/en-global/support/faqs/products/capacitor/mlcc/char/… and it states that "Without a DC voltage, spontaneous polarization can happen freely. However, when a DC voltage is externally applied, spontaneous polarization is tied to the direction of the electric field in the dielectric, and independent reversal of spontaneous polarization is inhibited. As a result, the capacitance becomes lower than before applying the bias.". So it's quite clear that when DC voltage decreases, the spontenous polarization (bigger capacity) is restored. \$\endgroup\$
    – Roger C.
    Commented Nov 26, 2014 at 15:57
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    \$\begingroup\$ @mkeith, sure, but it is always better if you can start with a reasonable theory (even if it might be not enough accurate or totally wrong) and challenge it through experimentation. \$\endgroup\$
    – Roger C.
    Commented Nov 27, 2014 at 11:22
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My comment may not be relevant to your specific problem but may be of some use.

I did some work on hold-up capacitor size inside power supplies, with my solution, energy stored in the hold-up capacitor is boosted by a step up dc-dc convertor, giving longer hold-up times and load power surges that would not otherwise be possible.

E=C*V^2 so the more volts the better. There are some technical notes and LTspice simulations in the document.

https://drive.google.com/file/d/0B4IxJOYnrSR6VXJtTDkwd3NLOUU/view?usp=sharing

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