# Gate capacitance vs. Gate charge in n-ch FETs, and how to calculate power dissipation during charging/discharging of the gate

I am using a MOSFET driver (TC4427A), which can charge a 1nF gate capacitance in about 30ns.

The dual N-ch MOSFET I am using (Si4946EY) has a gate charge of 30nC (max) per fet. I am only considering one for now as both on the die are identical. I am driving the gate to 5V. (It is a logic level fet.)

Does this mean I can apply Q = CV to work out the capacitance? C = 30nC / 5V = 6nF. So my driver can turn the gate fully on in about 180ns.

Is my logic correct?

Gate resistance of the MOSFET is specified at a max. of 3.6 ohms. Will this have any effect on the calculations above? The driver has a 9 ohm resistance.

Is there any significant difference for when the gate is discharged instead of charged? (turning off the fet.)

As a side question, during the 180ns the fet is not fully on. So Rds(not-quite-ON) is quite high. How can I calculate how much power dissipation will occur during this time?

• It looks like your switching time will be limited by the delay and switching time of the driver chip. There is little difference between on and off, the output stage of the driver chip is a totem pole driver. You can speed up the turn-off time with a diode. 30-40 ns is a very short time :-) If you are concerned about the power dissipation, you need to figure in how often you will be switching. – morten Jun 7 '11 at 21:52
• @morten: the OP is talking about driving a FET -- I thought the diode speed-up thing only applies to driving a BJT ? – davidcary Jul 26 '11 at 10:28
• The bounty will be awarded to the first answer which answers all my questions - turn on time, effect of gate & driver resistance, discharge/charge symmetry and Rds(not-quite-ON) – Thomas O Jul 26 '11 at 10:41

Like endolith says you have to look at the conditions for parameters. the 30nC are a maximum value for $V_{GS}$ = 10V. The graph on page 3 of the datasheet says typically 10nC @ 5V, then C = $\frac{10nC}{5V}$ = 2nF. Another graph also on page 3 gives a value of 1nF for $C_{ISS}$. The discrepancy is because capacitance isn't constant (that's why they give a charge value).

The gate resistance will indeed have an influence. The gate's time constant will be (9$\Omega$ + 3.6$\Omega$) $\times$ 2nF = 25ns, instead of 9$\Omega \times$ 2nF = 18ns.

In theory there will be a slight difference between switching on and off, because when switching off you start from a higher temperature. But if the time between on and off is small (lots of margin here, we talk about tens of seconds) temperature is constant, and the characteristic will be more or less symmetrical.

About your side question. This isn't usually given in datasheets, because the current will depend on $V_{GS}$, $V_{DS}$ and temperature, and 4-dimensional graphs don't work well in two dimensions. The only solution is to measure it. One way is to record $I_D$ and $V_{DS}$ graphs between off and on and, multiply both and integrate. This transition normally will happen fast, so you'll probably can measure only over a few points, but that should give you a good approximation. Doing the transition more slowly will yield more points, but the temperature will be different, and hence the result will be less accurate.

Referencing this Fairchild app note on MOSFET switching, this Infineon note on figure-of-merit, this IR note and my own experience:

$Q_g$ quantifies the total gate charge, which is comprised of some lumped elements:

• $Q_{gs}$ (gate-to-source)
• $Q_{gd}$ (gate-to-drain)

In terms of calculating how much power is dissipated switching the MOSFET on, you can use the Q=CV relation to figure out the effective gate capacitance. The manufacturer often also publishes this figure as$C_{iss}$.

The IR note sums up switching loss quite nicely. During the $Q_{gs}$ interval, the MOSFET starts conducting ($I_D$ ramps up and $V_{DS}$ stays high). During the $Q_{gd}$ interval, the MOSFET gets saturated ($V_{DS}$ falls). The best way to see the loss is, as was previously suggested, to measure $V_{DS}$ and $I_D$. This EETimes article describes how to mathematically calculate the switching loss for a variety of conditions, which I will not elaborate on here.

The MOSFET gate resistance is added with whatever external resistance you have to determine the charging current. In your case, since you're only charging to 5V, you will not max out the current capability of your driver.

Discharging the gate is relatively identical to charging it, in so far as the thresholds remain the same. If the turn-on thresold is 4V, and you charge to 5V, you can imagine that there will be some small asymmetry in the turn-on time vs. the turn-off time since you're only discharging 1V to get turn-off vs. 4V to get turn-on.

As per the earlier comment, it is quite common to see networks of resistors and diodes in MOSFET drive circuits to tailor the turn-on and turn-off charging currents.

The spec in the datasheet says VGS = 10 V, so no. It would be C = 30 nC / 10 V = 3 nF. But this is an absolute maximum.

Instead of a single capacitance value, they spec the capacitance as a graph on page 3. The meanings of ciss crss and coss are given in this document figure 5. I think you care most about ciss, which is about 900 pF according to the chart.

• -1 using Ciss, Crss, Coss to determine the gate capacitance to thus determine the switching losses is incorrect. Ciss,Crss,Coss is the small signal input/output capacitance – JonRB Dec 17 '13 at 23:46
• @Naib: How is the large signal capacitance different and where would you find a spec of it? – endolith Dec 18 '13 at 3:56
• Well Ciss, Crss, Coss is done with a Vgs=0V at around 1MHz... Qgate and thus Cgate must never be calculated from the IGBT or MOSFET input capacitance figures, these are merely 1st order approx of the gatecharge curve around the origin. The gate charge curve of switching devices are highly non-linear (fig5) That flat period is the miller plateu and appears as an inf capacitor. The 1st linear section of the charge curge is todo with charging the Gate-source, the flat period is countering the miller capacitor (Gate-drain). – JonRB Dec 18 '13 at 9:54
• @JonRB what would you then use to get an estimate of the input capacitance? It seems like Ciss would only be a valid estimate for Vgs from 0 until just before hitting the plateau voltage. And why are we given Ciss if we can instead use the gate charge to get a much closer approximation? – Big6 Feb 16 '17 at 13:57

power dissipation during turn-on and turn-off

You might think that the transistor getting hotter during those transitions has something to do with the internal voltages and currents and capacitances of the transistor.

In practice, as long as you turn a switch on or off sufficiently quickly, the internal details of the switch are irrelevant. If you pull the switch completely out of the circuit, the other stuff in the circuit inevitably has some parasitic capacitance C between the two nodes that the switch turns on and off. When you insert a switch of any kind into that circuit, with the switch off, that capacitance charges up to some voltage V, storing CV^2/2 watts of energy.

No matter what kind of switch it is, when you turn the switch on, all CV^2/2 watts of energy are dissipated in that switch. (If it switches really slowly, then perhaps even more energy is dissipated in that switch).

To calculate the energy dissipated in your mosfet switch, find the total external capacitance C it is attached to (probably mostly parasitic), and the voltage V that the terminals of the switch charge up to just before the switch turns on. The energy dissipated in any kind of switch is

• E_turn_on = CV/2

at each turn-on.

The energy dissipated in the resistances driving the gate your FET is

• E_gate = Q_g V

where

• V = the gate voltage swing (from your description, it's 5 V)
• Q_g = the amount of charge you push through the gate pin to turn on or off the transistor (from the FET data sheet, it's about 10 nC at 5 V)

The same E_gate energy is dissipated during turn-on, and again during turn-off.

Some of that E_gate energy is dissipated in the transistor, and some of it is dissipated in the FET driver chip -- I usually use a pessimistic analysis that assumes all of that energy is dissipated in the transistor, and also all of that energy is dissipated in the FET driver.

If your switch turns off sufficiently rapidly, the energy dissipated during turn-off is typically insignificant compared to energy dissipated during turn-on. You could place a worst-case bound (for highly inductive loads) of

• E_turn_off = IVt (worst case)

where

• I is the current through the switch just before turn-off,
• V is the voltage across the switch just after turn-off, and
• t is the switching time from on to off.

Then the power dissipated in the fet is

• P = P_switching + P_on

where

• P_switching = (E_turn_on + E_turn_off + 2 E_gate) * switching_frequency
• switching_frequency is the number of times per second that you cycle the switch
• P_on = IRd = the power dissipated while the switch is on
• I is the average current when the switch is on,
• R is the on-state resistance of the FET, and
• d is the fraction of the time that the switch is on (use d=0.999 for worst-case estimates).

Many H bridges take advantage of the (usually unwanted) body diode as a flyback diode to catch the inductive flyback current. If you do that (rather than using external Schottky catch diodes) you'll also need to add in the power dissipated in that diode.