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I have a breadboard circuit that controls some solenoid valves and am trying to move it to a PCB along with improving it for ESD and EMI.

This is the circuit I have on the breadboard that I want to add ESD protection to: enter image description here

Should I add the TVS diodes before or after the flyback diode?

So far, my thinking is that I should put them after because I want the coil discharge current to go through the flyback diode (which can sustain that current steady-state) instead of the TVS diodes.

Like this: enter image description here

Clarifications:

  • Everything below the blue line is on one board. Everything above the blue line is off board. There's a connector and a few feet of wire in between the two.

  • I'm mainly worried about ESD damaging the FET when people touch the connector to plug or unplug the cable. The only thing on the +12V net is more copies of this circuit for additional valves, so I don't think there's anything else sensitive there.

Basically my question is whether the left or right layout for the diodes better and why: enter image description here

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  • \$\begingroup\$ What are you specifically trying to "protect" and where is the EMI coming from? \$\endgroup\$ – Andy aka May 29 '15 at 8:24
  • \$\begingroup\$ I'd be more worried about ESD damaging the gate of the FET if this circuit is on a different board than the MCU. \$\endgroup\$ – John D May 29 '15 at 15:06
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I am not sure, what the question is, but i know what did you forget. You have also to protect the gate driver. This is because between the gate and the drain (and source) there is some capacitance which in case of ESD discharge will just conduct, so a voltage surge is possible on the gate.

upd. in case of such surge one of the implications may be opening the valve. not very nice.

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  • \$\begingroup\$ If an ESD spike comes down the connector and gets to the FET at all, haven't I already potentially damaged stuff? I figured that the ESD current needed to be shunted to the ground plane close to the connector and the FET would never see it. \$\endgroup\$ – Chris Dahlberg May 29 '15 at 21:24
  • \$\begingroup\$ First, who knows? It's kind of voodoo stuff, so it's better to be careful. Next, ESD damage is quite rare these days, so in particularly your application you might not seeing anything, no matter what protection you use. As for the specific protection i mentioned, the dominating factor is frequency, or if you want, rise time of the surge. Even if thanks to the tvs it's only 12v, but it's fast enough to pass the gate capacitance, it's there. \$\endgroup\$ – Gregory Kornblum May 29 '15 at 21:27
  • \$\begingroup\$ By the way, you asked about layout- left is better, eliminates inductance and capacitance of traces that in some cases may impede and prevent the protection from being fast enough. \$\endgroup\$ – Gregory Kornblum May 29 '15 at 21:30
  • \$\begingroup\$ Right of course :) it's my dyslexia. Place tvs closer to the connector. \$\endgroup\$ – Gregory Kornblum May 29 '15 at 21:36

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