Demultiplexor logic table simplification

Question

I need to implement simple demux in HDL:

Demultiplexer logic would be:

{a, b} = {in, 0} if sel == 0

{a, b} = {0, in} if sel == 1

I've started from basic logic table and first of all I wrote all posible combinations of all pins and in result i got:

/**
*   in | sel | a | b
*   ----------------
*   0  |  0  | 0 | 0
*   1  |  0  | 0 | 0
*   0  |  1  | 0 | 0
*   1  |  1  | 0 | 0
*   0  |  0  | 1 | 0
*   1  |  0  | 1 | 0
*   0  |  1  | 1 | 0
*   1  |  1  | 1 | 0
*   0  |  0  | 0 | 1
*   1  |  0  | 0 | 1
*   0  |  1  | 0 | 1
*   1  |  1  | 0 | 1
*   0  |  0  | 1 | 1
*   1  |  0  | 1 | 1
*   0  |  1  | 1 | 1
*   1  |  1  | 1 | 1
*/

Working on gate with single output i would need to build logical expression where output is equal to 1. Now I'm bit confused how to simplify this logic table even if I know how final result should look like:

/**
*   in | sel | a | b
*   -----------------
*   0  |  0  | 0 | 0
*   1  |  0  | 1 | 0
*   0  |  1  | 0 | 0
*   1  |  1  | 0 | 1
*/

It would be great to get an idea how it is simplified, thanks.

Answer 1

You are making a classic error.

You need to list the possible states of the input pins and the resulting outputs: you have listed the outputs as if they were inputs.

As there are only 4 possible combinations for the input pins, the final table you have is what you should have done originally.

/** * Input possibilities | Output result from requirement * in | sel | a | b * --------------------------- * 0 | 0 | 0 | 0 * 1 | 0 | 1 | 0 * 0 | 1 | 0 | 0 * 1 | 1 | 0 | 1 */

In verilog

    module demux1to2
    (in,
    sel,
    a,
    b);

    // inputs
    input in;
    input sel;

    // outputs
    output a;
    output b;

// I am using registers for the outputs

    reg a;
    reg b;

        always @(in or sel)
        begin
            // find sel
            case (sel)
                1'b0 : begin
                // a output selected
                a = in;
                b = 0;
                end

                1'b1 : begin
                // b output selected
                b = in;
                a = 0;
                end
            endcase
        end
 endmodule

Answer 2

Thanks @PeterSmith for helping me out. As he noticed above in the comment I've been making one mistake by listing the outputs as they were inputs.

Just to refresh demultiplexer logic would be:

{a, b} = {in, 0} if sel == 0

{a, b} = {0, in} if sel == 1

In case when we have more than single output we need:

• List possible states of the input pins
• Add resulting outpus to our logic table

Let's go through these steps.

1. List possible states of the input pins (in, sel ):

/**
*   in
*   --
*   0
*   1
*/

Let's add sel:

/**
*   in | sel
*   --------
*   0  | 0
*   1  | 0
*   0  | 1
*   1  | 1
*/

2. Add resulting outpus to our logic table:

/**
*   in | sel | a | b
*   ----------------
*   0  |  0  | 0 | 0  ---> {a, b} = {in, 0} if sel == 0; {a, b} = {0, 0};
*   1  |  0  | 1 | 0  ---> {a, b} = {in, 0} if sel == 0; {a, b} = {1, 0};
*   0  |  1  | 0 | 0  ---> {a, b} = {0, in} if sel == 1; {a, b} = {0, 0};
*   1  |  1  | 0 | 1  ---> {a, b} = {0, in} if sel == 1; {a, b} = {0, 1};
*/

That's it. :)