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I'm a beginner in FPGAs programming, and I've came across this issue recently:

In a synchronous process, what is the logical explanation for a signal not being able to be read right after its assignation? (I have an idea of the answer but I want to hear your take on this)

On the following snippet of VHDL code:

if byteCnt = 0 then                -- On the 1st clock cycle, I assign the first byte of data to block_count's MSByte
    block_count(15 downto 8) <= rx_data;
    byteCnt := byteCnt+1;
elsif byteCnt = 1 then             -- On the 2nd, the LSByte is assigned
    block_count(7 downto 0) <= rx_data;
    cmd_internal <= block_count;   -- Here cmd_internal = 10101010UUUUUUUU, why?
end if;

A quick workaround would be cmd_internal <= block_count(15 downto 8) & rx_data; but that's not the point of my question :)

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  • \$\begingroup\$ Edit your question to include your idea of the answer, that will help us understand your though processes. \$\endgroup\$
    – Tom Carpenter
    Commented Jul 21, 2016 at 12:46
  • \$\begingroup\$ Ok will do! Was I clear enough on what's happening here? \$\endgroup\$
    – Fluffy
    Commented Jul 21, 2016 at 12:48
  • \$\begingroup\$ I believe so. What you are describing is the expected behaviour of synchronous logic. \$\endgroup\$
    – Tom Carpenter
    Commented Jul 21, 2016 at 12:50
  • \$\begingroup\$ After reading further on this, from my understanding, the logic vector is stored in D flops. So in order to update its value, it needs one clock cycle. That's why it reads "Unassigned" right away, is that correct? \$\endgroup\$
    – Fluffy
    Commented Jul 21, 2016 at 12:55

1 Answer 1

Reset to default
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Since you are talking about a clocked signal assignment your code is inferring a D Flop register. From the diagram below, it should be clear that the current input (D) on any given clock will not be available for reading (Q) on the same clock edge.

D Flop

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