VHDL: Signal assignment question

Question

TLDR: The specific ordering question I'm asking is:

1. Suppose the output depends on some intermediate signals
2. Suppose the intermediate signals depend on some input signals
3. Suppose an input signal changes
4. This may make more than one intermediate signal change
5. The timing of signal assignment is not stringently specified
6. If the output signal generation function observes one of the intermediate signals as having changed before the other intermediate signals having changed, a "transient" output may be generated until the change in the second intermediate signal is observed.
7. Does VHDL guarantee that this does not happen? If so, how?

Reading through the Free Range VHDL book, on page 37, there is a code snippet that is claimed to be equivalent to the code snippet on page 36:

-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- entity
entity my_ckt_f3 is
port ( L,M,N : in std_logic;
F3 : out std_logic);
end my_ckt_f3;
-- architecture
architecture f3_2 of my_ckt_f3 is
begin
F3<=((NOT L)AND(NOT M)AND N)OR(L AND M);
end f3_2;

versus:

-- library declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- entity
entity my_ckt_f3 is
port ( L,M,N : in std_logic;
F3 : out std_logic);
end my_ckt_f3;
-- architecture
architecture f3_1 of my_ckt_f3 is
signal A1, A2 : std_logic; -- intermediate signals
begin
A1 <= ((NOT L) AND (NOT M) AND N);
A2 <= L AND M;
F3 <= A1 OR A2;
end f3_1;

But! The description in the text claims that signals are delayed assignment ("some time" after) and timing or ordering is not guaranteed.

In my mind, this translates to approximately something like "the right side is sampled on clock-rising, and the left side is written on clock-falling," although I'm sure different implementations are actually used in reality.

Now, assuming that each <= operator in a logic chain introduces a time delay of undetermined amount, why are these two snippets equivalent? Couldn't it be that the second implementation, with temporary signals, temporarily outputs some logic value that is not actually the result of any combination of the inputs that it has seen?

I guess I'd like a more formal understanding of what the "signal assignment" really means for timing and outputs. Are compilers guaranteed to "optimize" or "short circuit" temporary signal assignments so that the end result will always be the same as if I wrote the logic expression on a single line?

Answer 1

If you are wondering about how the <= operator works; it is what is called a 'nonblocking assignment.' What this means is that the left hand side of all of the <= are performed for a particular event (e.g. rising clock edge) and then once those are all evaluated, the result is placed in the output. This allows you to write shift registers without temporary variables. None of the values change until the left hand calculations are completed, then the results are moved over to the right hand side. It is generally not a good idea to use nonblocking assignments for combinatorial logic. Generally they are only used to create latches and registers and you use regular blocking assignments for combinatorial logic. When synchronized with a clock signal, you can generally consider <= operations to be D flip-flops that sample the input and transfer it to the output atomically on a single clock edge.

'Race conditions' where intermediate indeterminate results appear on the outputs of combinatorial functions are hard to avoid and they can depend greatly on how the design is actually implemented on an ASIC or FPGA. However, most designs are synchronous and so as long as the output settles within one clock period this is not a problem. There are tools that can check the timing performance of a design to check all of the path delays to ensure that the results will always be valid for a given clock frequency, but this is highly dependent not on the actual HDL code but on the way the design is placed and routed.

Synthesizers (not compilers!!!!) will generally perform optimization on combinatorial logic. There are limits to how much the synthesizer can do (e.g. it will not re-architect your system) so you have to know more or less how it will end up being implemented. If you're working on an FPGA, generally the synthesis and place and route will pack any logic function that fits onto LUTs. So if you can separate out a single logic function with up to 4 inputs and 1 output, this will end up on a single LUT and the only delay that matters is the propagation delay of the LUT, which is the same for all of its inputs. In the case of your example function, both pieces of code may be implemented identically on one LUT with three inputs and one output.