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In my ASIC book they are developing a state machine, and they have a statement like:

 Shift <= '1' when State = S else '0'; 

However in my project I have multiple states that have the same output being required to turn on so is it possible to write VHDL like this:

 Shift <= '1' when State = S OR State = E OR STATE = Q else '0'; 

Or do I have to assign Shift for each of my states?

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Yes that is doable

Shift <= '1' when ((State = S) OR (State = E) OR (STATE = Q))
             else '0'; 
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  • \$\begingroup\$ The parentheses are unnecessary; the code in the question was already correct. \$\endgroup\$ – Brian Drummond Feb 12 '14 at 14:35
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    \$\begingroup\$ @BrianDrummond I think it's a good habit to parenthesize conditions in any "programming" language, it makes things much clearer. \$\endgroup\$ – alexan_e Feb 12 '14 at 14:48
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    \$\begingroup\$ @alexan_e: although some take the view that excessive parens are less clear... I would certainly remove the outer parens \$\endgroup\$ – Martin Thompson Feb 12 '14 at 16:34

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