In my ASIC book they are developing a state machine, and they have a statement like:

 Shift <= '1' when State = S else '0'; 

However in my project I have multiple states that have the same output being required to turn on so is it possible to write VHDL like this:

 Shift <= '1' when State = S OR State = E OR STATE = Q else '0'; 

Or do I have to assign Shift for each of my states?


1 Answer 1


Yes that is doable

Shift <= '1' when ((State = S) OR (State = E) OR (STATE = Q))
             else '0'; 
  • \$\begingroup\$ The parentheses are unnecessary; the code in the question was already correct. \$\endgroup\$
    – user16324
    Commented Feb 12, 2014 at 14:35
  • 1
    \$\begingroup\$ @BrianDrummond I think it's a good habit to parenthesize conditions in any "programming" language, it makes things much clearer. \$\endgroup\$
    – alexan_e
    Commented Feb 12, 2014 at 14:48
  • 1
    \$\begingroup\$ @alexan_e: although some take the view that excessive parens are less clear... I would certainly remove the outer parens \$\endgroup\$ Commented Feb 12, 2014 at 16:34

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.