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We are writing a code using vhdl. Please tell us elaborately how to add the fixed_pkg code into the ieee_proposed library.

The fixed package is probably found here: here. Is this the fixed_pkg code that we have to add?

We are trying to make the following code work:

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 08/01/2016 03:49:02 PM
-- Design Name: 
-- Module Name: fixed_point1 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;


--use ieee.fixed_pkg.all;


entity fixed_point1 is
    Port ( a,b : in STD_LOGIC;
           c : in STD_LOGIC;
           d : in STD_LOGIC_VECTOR (3 downto 0));
end fixed_point1;

architecture Behavioral of fixed_point1 is
signal example : ufixed (3 downto -4);
begin
example <= "10011100";

end Behavioral;

This code is synthesised properly.However during simulation it is giving some compilation error( 'fixed_pkg' is not compiled in library ieee_proposed [../../../fixed_point1.srcs/sources_1/new/fixed_point1.vhd:26]). Please tell us elaborately how to compile fixed_pkg in ieee_proposed so that the simulation works.

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    \$\begingroup\$ As I said in my previous comment, here, electronics.stackexchange.com/questions/249052/… , you don't need to do this if your simulator supports VHDL-2008. And if it doesn't, you just need to compile the relevant source files into the relevant library. \$\endgroup\$
    – user16324
    Commented Aug 2, 2016 at 10:13

1 Answer 1

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For most of the common tools, only standard libraries are pre-compiled. That means it is probably not the case with the one you're using.

To solve your issue I advise you to add the pkg "by hand". Create a custom package, copy all the content that you need (or simply import the whole file into your workspace) and add it manually to your design using:

USE WORK.ieee_proposed.ALL;

Hope it helped.

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