VHDL how to code a Mealy NSTT

Question

Noob here, I remember back in school learning how to code a Mealy next state transition table and deriving this equation using k-maps and then coding the actually equations for all the outputs rather than coding states with a bunch of if-else statements.

I found here how to setup the tables and kind of derive the equations but what's next? How do I implement these into the current_state and next_state's and program the output logic equations?

I've searched far and wide online and I can't find a thing on it. Is there a certain name for this? Maybe I'm Googling the wrong thing?

Any info, examples and guidance will be appreciated.

Answer 1

I will expand on the comments posted here by showing you how to code a VHDL state machine so that the tools compute these transition tables.

library ieee;
use ieee.std_logic_1164.all;

entity SimpleFSM is
  port (
    clk : in std_logic;
    input : in std_logic;
    output : out std_logic
  );
end entity SimpleFSM;

architecture fsm of SimpleFSM is
  -- This type represents all of your states by name
  type state_t is (
    STATE_BEGIN,
    STATE_END
  );
  -- And this is signal which holds the current state.
  signal state : state_t := STATE_BEGIN;
begin
  process (clk)
  begin
    if rising_edge(clk) then
      case (state) is
        -- This is to say, if the current state is 'STATE_BEGIN'
        when STATE_BEGIN =>
          -- You can change the output based on the state.
          -- NOTE that this is one cycle delayed from when you entered the state.
          -- To change the output on the same cycle,
          -- use some combinational logic outside the process.
          output <= '0';
          -- This is your transition logic. Much easier to read, I think.
          -- Any logic suitable for a process (such as an if-elsif-else chain)
          -- can be used to make this choice,
          -- and the tools (simulator, synthesis) will calculate a transition function for you.
          if (input = '1') then
            state <= STATE_END;
          end if;
          -- By default, it stays in the same state
        when STATE_END =>
          output <= '1';
          if (input = '0') then
            state <= STATE_BEGIN;
          end if;
      end case;
    end if;
  end process;
end fsm;